Abstract: An electronic device with a camera anti-peeping structure includes a main body, a camera and an anti-peeping structure. The anti-peeping structure includes a mounting member, a sliding member and an anti-peeping piece. The sliding member is slidably disposed in a groove of the sliding member. The sliding member includes a first magnet. The anti-peeping piece includes a first end with a second magnet and a second end. The second end is pivotable based on the first end. When the sliding member moves to the first position, the first magnet attracts the second magnet such that the second end of the anti-peeping piece pivots toward the sliding member to expose the camera. When the sliding member moves to the second position, the first magnet repels the second magnet repel such that the second end of the anti-peeping piece pivots away from the sliding member to cover the camera.

Abstract: A coil device includes a core and a plurality of coils arranged in the core. A distance of a second gap formed by portions of the core located inside at least one of the coils is larger than that of a first gap formed by other portions of the core located between the coils next to each other.

Abstract: A coil device includes a pair of first core and second core, a third core, and a pair of first coil and second coil. The third core is disposed next to the first core or the second core. The pair of first coil and second coil is each disposed between any two of the first core, the second core, and the third core next to each other. Plate surfaces of the first coil and the second coil are opposed to each other. Each of the first coil and the second coil is partly exposed in a lateral direction of the first core, the second core, or the third core.

Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes: a photosensitive sensor; a light shield layer disposed on a sensing side of the photosensitive sensor and including at least one first opening and at least one second opening, the first opening and the photosensitive sensor are overlapped with each other in a direction perpendicular to a surface of the display panel, so that light running through the first opening is irradiated to the photosensitive sensor; and an optical processing film disposed in a region of the light shield layer close to the second opening and on at least a portion of a surface of the light shield layer away from the photosensitive sensor, and a light reflectivity of the optical processing film is less than a light reflectivity of the light shield layer.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

Abstract: An insulation resistance detection circuit and method are disclosed. The circuit includes a controller configured to: open a first relay, and close second relays, or switch an on/off status of at least one of the second relays; determine, based on a first measurement value between a positive input terminal of an inverter circuit and an earthing point, whether the positive input terminal of the inverter circuit is short-circuited or has low resistance to protective earthing; and determine, based on a second measurement value between a negative input terminal of the inverter circuit and the earthing point, whether the negative input terminal of the inverter circuit is short-circuited or has low resistance to protective earthing, where the first relay is one of in M relays and is connected to at least one impedor in parallel, and the second relays are relays other than the first relay in the M relays.

Abstract: A method for providing automatic restatement of a data environment includes receiving a request for restatement of a first dataset, accessing dependency data that describes a set of dependencies between the first dataset and one or more other datasets in the computer data environment, examining the dependency data to automatically identify one or more second dataset from among the one or more other datasets, the second datasets being datasets from which the first dataset depends, examining a first timing data related to the restatement of the first dataset and a second timing data related to the restatement of the identified second datasets to identify one or more third datasets from among the second datasets that require restatement as a result of the restatement of the first dataset, generating a restatement plan based on the identified third datasets, and initiating automatic execution of the restatement plan.

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

Abstract: Embodiments of the present disclosure disclose an information display method and apparatus, and an electronic device. The method in a specific embodiment comprises: receiving a multimedia information stream, wherein the information stream comprises a multimedia data stream, and interactive information sent by a user according to multimedia information content; determining data types corresponding to the interactive information, the data types comprising an emoji data type and a chat data type; and in response to determining that the interactive information is to be displayed on a display interface displaying the multimedia data stream, displaying the interactive information on the display interface in an interactive information display region corresponding to the data types, the interactive information display region comprising a chat information display region and an emoji information display region.

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.