Patents by Inventor Chen An Wu

Chen An Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145670
    Abstract: A negative electrode structure applied to an aluminum battery includes a hole material layer and a metal plating layer. The metal plating layer is located on the hole material layer such that the capacity decay rate of the aluminum battery is less than 5% per cycle.
    Type: Application
    Filed: May 31, 2023
    Publication date: May 2, 2024
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Wei-An Chen
  • Publication number: 20240145706
    Abstract: The present invention provides a core-shell cathode characterized by comprising: a shell comprising an electrically conductive, porous carbon material; and a core, which is an inner cavity enclosed within the shell, wherein the core contains an active material and an electrolyte, and the active material comprises liquid polysulfide having the general formula Li2Sx, wherein 4?x?8; the shell comprises a first layer, an O-ring and a second layer sequentially stacked from bottom to top to form the inner cavity to contain the active material and the electrolyte. The present invention also provides a lithium-sulfur battery using said core-shell cathode, which attains both high sulfur loading and high sulfur content, and simultaneously satisfies high energy density, high capacity retention and high cycle stability under lean-electrolyte condition.
    Type: Application
    Filed: December 23, 2022
    Publication date: May 2, 2024
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Sheng-Heng CHUNG, Yun-Chen WU
  • Publication number: 20240143141
    Abstract: The present disclosure generally relates to underwater user interfaces.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Benjamin W. BYLENOK, Alan AN, Richard J. BLANCO, Andrew CHEN, Maxime CHEVRETON, Kyle B. CRUZ, Walton FONG, Ki Myung LEE, Sung Chang LEE, Cheng-I LIN, Kenneth H. MAHAN, Anya PRASITTHIPAYONG, Alyssa RAMDYAL, Eric SHI, Xuefeng WANG, Wei Guang WU
  • Publication number: 20240141476
    Abstract: A method for manufacturing a target material is provided, including the steps of: disposing raw material powder on a substrate and melting the raw material powder by laser to form a target material layer; repeating the preceding process to allow a plurality of target material layers to form an integrated target material column; after cooling the target material column, removing the target material column from the substrate; and performing vacuum heat treatment on the target material column. Since the target material is additively manufactured and subjected to vacuum heat treatment, the target material has a finer and more uniform microstructure, thus improving the product quality.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: TAIWAN STEEL GROUP AEROSPACE ADDITIVE MANUFACTURING CORPORATION
    Inventors: William HSIEH, Bo-Chen Wu, Chii-Feng Huang, Jun-Cheng Wang
  • Patent number: 11971451
    Abstract: A method includes: constructing an on-wafer calibration piece model set that includes one or more on-wafer calibration piece models, where each of the one or more on-wafer calibration piece models has a corresponding on-wafer calibration piece; selecting an on-wafer calibration piece model from the on-wafer calibration piece model set; measuring the on-wafer calibration piece utilizing an on-wafer S parameter measurement system that is calibrated using a multi-thread TRL calibration method in a Terahertz frequency band, to obtain an S parameter of the on-wafer calibration piece; and calculating a plurality of different parameters that represent crosstalk of calibration pieces in the on-wafer calibration piece model, according to an admittance calculated according to the S parameter and an admittance formula corresponding to the on-wafer calibration piece model.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 30, 2024
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Aihua Wu, Yibang Wang, Faguo Liang, Chen Liu, Ye Huo, Peng Luan, Jing Sun, Yanli Li
  • Patent number: 11973297
    Abstract: An electrical connector including an insulating body, a first metallic member, a second metallic member, a plurality of terminals, and a metallic shell is provided. The insulating body has a base portion, a thickened step portion, and a tongue portion. The thickened step portion is located at a root of the base portion. The first metallic member and the second metallic member are disposed on an upper surface and a lower surface of the insulating body. The metallic shell is disposed on an exterior of the insulating body to surround the first metallic member, the second metallic member, and the terminals, wherein the front flat contact portion of each of the terminals is exposed out of the tongue portion, and a portion of the first metallic member and a portion of the second metallic member are exposed out of the thickened step portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: April 30, 2024
    Assignee: Advanced Connectek Inc.
    Inventors: Chingtien Chen, Wei Wan, Hua-Yan Wu
  • Patent number: 11972971
    Abstract: A wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. This enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. A controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. This enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Chen, Yi-Fam Shiu, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11970246
    Abstract: A ship cabin loading capacity measurement method and apparatus thereof, comprises: acquiring point cloud measurement data of a ship cabin; optimizing the point cloud measurement data according to a predetermined point cloud data processing rule, and generating optimized ship cabin point cloud data; calculating said ship cabin point cloud data with a predetermined loading capacity calculation rule, and getting ship cabin loading capacity data. According to the ship cabin loading capacity measurement method of the present invention, the point cloud measurement data can be acquired by a lidar, and processing the point cloud measurement data of the ship cabin with a predetermined point cloud data processing law and a computation law, and as the point cloud data processing law and the computation law can be deployed in a computer device in advance, after point cloud measurement data acquisition, loading capacity of a ship cabin can be acquired quickly and precisely.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: April 30, 2024
    Assignee: Zhoushan Institute of Calibration and Testing for Quality and Technology Supervision
    Inventors: Huadong Hao, Cunjun Li, Xianlei Chen, Haolei Shi, Ze'nan Wu, Junxue Chen, Zhengqian Shen, Yingying Wang, Huizhong Xu
  • Publication number: 20240137522
    Abstract: A method for processing a screen content video. The screen content video includes a plurality of frames each including a plurality of coding tree units and a plurality of coding units in each of the coding tree units. The method includes performing a coding-tree-unit-based analysis operation on the screen content video to determine content information associated with the screen content video, and performing a rate control operation on the screen content video based on the determined content information to encoding of the screen content video. The content information includes content complexity information associated with the screen content video and temporal importance information associated with the screen content video.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 25, 2024
    Inventors: Sam Tak Wu Kwong, Yi Chen, Shiqi Wang
  • Publication number: 20240131168
    Abstract: Anaphthalene ring-containing compound, a pharmaceutical composition containing same, and the use thereof. A naphthalene ring-containing compound as represented by formula III, a pharmaceutically acceptable salt thereof, a solvate thereof, or a solvate of the pharmaceutically acceptable salt thereof. The compound is new in structure and has a better activity on cancers.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 25, 2024
    Inventors: Liang WU, Yijun DENG, Zhenhua HE, Qiaoling SUN, Chen ZHOU, Tielin WANG
  • Publication number: 20240136376
    Abstract: A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.
    Type: Application
    Filed: March 10, 2023
    Publication date: April 25, 2024
    Inventors: DONG-RU WU, CHIEN-CHEN LEE, LI-CHUN HUNG
  • Publication number: 20240132083
    Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.
    Type: Application
    Filed: October 23, 2022
    Publication date: April 25, 2024
    Inventors: Anitha Kalva, Jae Wu, Shantanu Sarangi, Sailendra Chadalavada, Milind Sonawane, Chen Fang, Abilash Nerallapally
  • Patent number: 11967622
    Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11967272
    Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 23, 2024
    Assignees: AUO Corporation, National Cheng-Kung University
    Inventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
  • Patent number: 11965217
    Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
  • Publication number: 20240124163
    Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 18, 2024
    Applicant: National Cheng Kung University
    Inventors: Yueh-Heng Li, Yu-Ting Wu, Chao-Wei Huang, Wei-Cheng Lo, Hsun-Chen Hsieh, Ping-Han Huang, Yi-Long Huang, Sheng-Wen Liu, Wei-Cheng Lien
  • Publication number: 20240128333
    Abstract: A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Inventors: Ruilong Xie, Julien Frougier, Chen Zhang, Min Gyu Sung, Heng Wu
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11959826
    Abstract: The disclosure is an engine simulation test device capable of realizing an ultrahigh compression temperature and pressure, belonging to the field of a diesel engine high-temperature and high-pressure system, solving the problems that the existing engine simulation test cannot achieve ultra-high compression temperature and pressure, and the temperature and pressure are not adjustable. It includes a compressed air inlet mechanism, a nitrogen gas inlet mechanism, a pressure stabilizing mechanism, a cyclic heating mechanism, an air inlet mechanism and a fast compressor mechanism.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 16, 2024
    Assignee: HARBIN ENGINEERING UNIVERSITY
    Inventors: Long Liu, Yue Wu, Dai Liu, Qian Xiong, Xinru Shi, Shihai Liu, Chen An, Qihao Mei
  • Patent number: 11963420
    Abstract: There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 16, 2024
    Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Chen Xu, Xueguang Hao, Yong Qiao, Xinyin Wu