Patents by Inventor Chen An

Chen An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230064591
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration including a plurality of codebook subset restrictions. The UE may identify a codebook subset restriction, of the plurality of codebook subset restrictions, to be applied to precoding matrix indicator (PMI) selection associated with a slot. The UE may transmit a channel state information (CSI) report including an indication of a PMI selected based at least in part on the identified codebook subset restriction. Numerous other aspects are described.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: Abdelrahman Mohamed Ahmed Mohamed IBRAHIM, Muhammad Sayed Khairy ABDELGHAFFAR, Ahmed Attia ABOTABL, Wanshi CHEN, Huilin XU, Krishna Kiran MUKKAVILLI
  • Publication number: 20230062718
    Abstract: A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low- cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.
    Type: Application
    Filed: August 1, 2022
    Publication date: March 2, 2023
    Inventor: Yung-Tin Chen
  • Publication number: 20230067690
    Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a semiconductor device, a ring structure, a lid structure, and an adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in a gap between the ring structure and the semiconductor device and attached to the lid structure and the substrate.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen YEH, Chin-Hua WANG, Po-Chen LAI, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20230068596
    Abstract: A portable gas water maker comprises a water maker body with a shell having a hollow structure. A water inlet communicating with the shell and used for injecting water into the shell is formed at an upper end of the water maker body. The water maker body is inverted U-shaped, so that the lower half part of the water maker body is divided into a left cavity and a right cavity. One group of Peltier semiconductor assemblies is arranged in each of the left cavity and the right cavity. A front-end semiconductor and a rear-end semiconductor in each group of Peltier semiconductor assemblies are connected through a wire. The group of semiconductor assemblies in the left cavity is used for generating electricity, and the group of semiconductor assemblies in the right cavity is used for refrigeration.
    Type: Application
    Filed: August 23, 2022
    Publication date: March 2, 2023
    Applicant: XIJING UNIVERSITY
    Inventors: Kai CHEN, Qian ZHANG, Yao QIN, Xinfei LIU, Chenbo ZHANG, Wei ZHANG
  • Publication number: 20230066318
    Abstract: Augmented reality (AR) systems, devices, media, and methods are described for capturing and presenting effort put into generating a handcrafted AR experience. AR object generation data is captured during the generation of a handcrafted AR object. The AR object generation data is then processed to generate proof of effort data for inclusion with the handcrafted AR object. Examples of proof of effort include a time lapse view of the steps taken during generation of the AR object and statistics such as total time spent, number of images or songs considered for selection, number of actions implemented, etc.
    Type: Application
    Filed: August 16, 2022
    Publication date: March 2, 2023
    Inventors: Tianying Chen, Timothy Chong, Sven Kratz, Fannie Liu, Andrés Monroy-Hernández, Olivia Seow, Yu Jiang THAM, Rajan Vaish, Lei Zhang
  • Publication number: 20230067621
    Abstract: An electronic device having at least one circuit board. The circuit board has a predetermined pattern of solder bumps facilitating a ground connection with a first enclosure member and/or a second enclosure member. The at least one circuit board is sandwiched between the first and second enclosure members, each of the first and second enclosure members has a surface facing the circuit board and the surface facing the circuit board has a bead extending therefrom contacting the predetermined pattern of solder bumps to complete the ground connection.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Applicant: Harman International Industries, Incorporated
    Inventors: Jianing Chen, Jon Curry, David Jia
  • Publication number: 20230069382
    Abstract: Responsive to receiving a table flush command, a first portion of an address mapping table is identified. A first flush operation with respect to a first portion of the address mapping table is performed. Responsive to receiving at least one memory access command, flush operations for a subsequent portion of the address mapping table is suspended. At least one memory access operation specified by the at least one memory access command is performed. A second flush operation with respect to the subsequent portion of the address mapping table is performed.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yuehhung Chen, Chih-Kuo Kao, Fangfang Zhu, Jiangli Zhu
  • Publication number: 20230066870
    Abstract: A deposition system is provided capable of extending the chamber running time by preventing the target and other components from deformation due to thermal stress from the sputtering process by maintaining the temperature within the predetermined temperature range. The deposition system includes a substrate process chamber, a target within the substrate process chamber, and a plurality of grooves formed on the target in a circular formation. The plurality of grooves includes a first groove on a center portion of the target and a second groove on a periphery portion of the target.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Hsi WANG, Yen-Yu CHEN
  • Publication number: 20230062426
    Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Wei-De HO, Pei-Sheng TANG, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN, Chen-Jung WANG
  • Publication number: 20230062623
    Abstract: A positioning cutter/collet assembly has a cutter/collet and a magnetic attracting position key. The cutter/collet has a cutter/collet key seat recessed in an external annular surface thereof. The magnetic attracting position key is mounted on and magnetically attracts the cutter/collet key seat. The magnetic attracting position key has a body having a protruding rod and a magnetic attracting portion combined with the body and magnetically attracting the cutter/collet to prevent the magnetic attracting position key from separating from the cutter/collet.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Applicant: SHIN-YAIN INDUSTRIAL CO., LTD.
    Inventor: PEN HUNG CHEN
  • Publication number: 20230064912
    Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for generating a first scrambling identification (ID), generating a first scrambling sequence based on the first scrambling ID, scrambling a first set of information based on the first scrambling sequence to generate a first plurality of information bits, generating a plurality of repeated copies of the first plurality of information bits scrambled using the first scrambling sequence, and transmitting a first transmission burst including each of the plurality of repeated copies of the first plurality of information bits on different ones of a first plurality of resources in a communication channel.
    Type: Application
    Filed: April 3, 2020
    Publication date: March 2, 2023
    Inventors: Jing LEI, Chao WEI, Wanshi CHEN, Huilin XU, Peter Pui Lok ANG, Peter GAAL, Hwan Joon KWON, Krishna Kiran MUKKAVILLI, Tingfang JI
  • Publication number: 20230064894
    Abstract: A sole structure for an article of footwear comprises a midsole body having a proximal surface and a distal surface. Proprioceptive elements may extend in the hole in the midsole body, and translate toward the proximal surface in the holes upon a force directed along a central axis of the hole at a distal end of the proprioceptive elements. In various embodiments, the holes may angle relative to vertical from the proximal surface to the distal surface, the holes may be defined by perforations and the proprioceptive elements may be integral portions of the midsole body, or the midsole body may have a plurality of annular holes at the proximal surface, and a plurality of annular recesses in the distal surface, and a plurality of proprioceptive elements, each centered in a different annular hole of the plurality of annular holes. Methods of manufacturing articles of footwear are described.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 2, 2023
    Applicant: NIKE, Inc.
    Inventors: Yuchung K. Chen, Oliver McLachlan, Thomas J. Rushbrook, Timothy J. Smith
  • Publication number: 20230062872
    Abstract: A formulation for oral administration comprises an expectorant, an analgesic, and at least one additional active ingredient having a modified release providing a therapeutic effect for each of the active ingredients for up to 12 hours.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 2, 2023
    Inventors: Raghu Cavatur, Kevin Chen, Matthew Kaser, Hongchun Qiu, Ernest Joseph Woodhouse, Josef Borovicka, Elliot Wilkinson
  • Publication number: 20230067914
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
  • Publication number: 20230067967
    Abstract: In a method of inspecting an extreme ultraviolet (EUV) radiation source, during an idle mode, a borescope mounted on a fixture is inserted through a first opening into a chamber of the EUV radiation source. The borescope includes a connection cable attached at a first end to a camera. The fixture includes an extendible section mounted from a first side on a lead screw, and the camera of the borescope is mounted on a second side, opposite to the first side, of the extendible section. The extendible section is extended to move the camera inside the chamber of the EUV radiation source. One or more images are acquired by the camera from inside the chamber of the EUV radiation source at one or more viewing positions. The one or more acquired images are analyzed to determine an amount of tin debris deposited inside the chamber of the EUV radiation source.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chiao-Hua CHENG, Sheng-Kang YU, Shang-Chieh CHIEN, Wei-Chun YEN, Heng-Hsin LIU, Ming-Hsun TSAI, Yu-Fa LO, Li-Jui CHEN, Wei-Shin CHENG, Cheng-Hsuan WU, Cheng-Hao LAI, Yu-Kuang SUN, Yu-Huan CHEN
  • Publication number: 20230062128
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Shu-Wei LI, Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
  • Publication number: 20230066562
    Abstract: A battery includes a protective box provided with a guiding channel and a plurality of battery cells in the protective box. The plurality of battery cells include a first battery cell and a second battery cell adjacent to each other. The first battery cell includes a pressure relief end provided with a pressure relief mechanism. The pressure relief mechanism is configured to actuate release of internal pressure of the first battery cell in response to the internal pressure or an internal temperature of the first battery cell reaching a threshold. The guiding channel is configured to guide emissions released from the pressure relief mechanism. The pressure relief end of the first battery cell is staggered with one end of the second battery cell that is close to the pressure relief end, in a direction leaving the guiding channel.
    Type: Application
    Filed: November 11, 2022
    Publication date: March 2, 2023
    Inventors: Chengdu LIANG, Xiaofu XU, Yonghuang YE, Haizu JIN, Wenwei CHEN, Qian LIU
  • Publication number: 20230067563
    Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling an conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei SU, Chia-Tien WU, Hsin-Ping CHEN, Shau-Lin SHUE
  • Publication number: 20230065640
    Abstract: Provided are combination therapies and secondary biomarkers for treating MYCC-associated diffuse large B-cell lymphoma (DLBCL) with YM155-based therapies, and related kits, compositions, and methods of use thereof.
    Type: Application
    Filed: February 5, 2021
    Publication date: March 2, 2023
    Inventors: Xiang LI, Yiyou CHEN
  • Publication number: 20230060371
    Abstract: A camera module and a molded photosensitive assembly and manufacturing methods thereof, and an electronic device are disclosed. The molded photosensitive assembly includes an imaging assembly, a molded base and a filter assembly. The imaging assembly includes a circuit board and at least one photosensitive element, and each photosensitive element is conductively connected to the circuit board. The molded base has at least one stepped peripheral groove to define a light window through each stepped peripheral groove, the molded base embeds a part of the imaging assembly, and a photosensitive region of each photosensitive element respectively corresponds to each light window of the molded base. The filter assembly includes at least one filter element, and each filter element is correspondingly arranged in each stepped peripheral groove of the molded base, so that each filter element respectively corresponds to each light window of the molded base.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 2, 2023
    Inventors: Zhen HUANG, Qimin MEI, Bojie ZHAO, Zhewen MEI, Li LIU, Jiawei CHEN, Chenxiang XU