Patents by Inventor Chen-Chao Wang

Chen-Chao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220143001
    Abstract: The present invention provides a novel pan-RAF kinase inhibitor, comprising a compound of formula (I) or a pharmaceutically acceptable salt, solvate, ester, acid, metabolite or prodrug thereof. The present invention also provides a use or method of the compound of formula (I) in the treatment or prevention of a disorder related to the activity of RAF and/or RAS kinase.
    Type: Application
    Filed: March 7, 2019
    Publication date: May 12, 2022
    Applicant: TARAPEUTICS SCIENCE INC.
    Inventors: Qing Song LIU, Jing LIU, Xi Xiang LI, Ao Li WANG, Zi Ping QI, Qing Wang LIU, Zong Ru JIANG, Feng Ming ZOU, Wen Chao WANG, Chen HU, Cheng CHEN, Li WANG
  • Patent number: 11328999
    Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fu-Chen Chu, Hung-Chun Kuo, Chen-Chao Wang
  • Publication number: 20220139824
    Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Yi HUANG, Chen-Chao WANG, Mi-Chun HUNG
  • Publication number: 20220115276
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG
  • Patent number: 11232998
    Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 25, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Fong Jhong, Chen-Chao Wang, Hung-Chun Kuo
  • Patent number: 11222845
    Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: January 11, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-I Wu, Chen-Chao Wang
  • Publication number: 20210361565
    Abstract: An oral pharmaceutical composition comprising telmapitant, a non-aqueous solvent and one or more additional pharmaceutical acceptable excipients wherein the telmapitant is in solution in the composition. A method of treatment or prevention of emesis in animals comprising administering the oral pharmaceutical composition.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 25, 2021
    Applicant: Intervet Inc.
    Inventor: Chen-Chao Wang
  • Publication number: 20210278457
    Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
  • Publication number: 20210202353
    Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Fong JHONG, Chen-Chao WANG, Hung-Chun KUO
  • Publication number: 20210175175
    Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fu-Chen CHU, Hung-Chun KUO, Chen-Chao WANG
  • Publication number: 20210104461
    Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Chen-Chao WANG
  • Patent number: 10916429
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10903152
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • Patent number: 10903561
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee
  • Patent number: 10886263
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
  • Publication number: 20200335858
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE
  • Publication number: 20200111671
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Publication number: 20200083591
    Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE, Chien-Hua CHEN
  • Patent number: 10535521
    Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: January 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10515806
    Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the sec
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang