Patents by Inventor Chen-Chao Wang

Chen-Chao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104461
    Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Chen-Chao WANG
  • Patent number: 10903152
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • Patent number: 10647700
    Abstract: An inhibitor of a wild type and Y641F mutant of human histone methyltransferase EZH2 is provided herein. Particularly, the inhibitor is a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. The inhibitor can be used to treat a cancer or precancerous condition related to EZH2 activity.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TARAPEUTICS SCIENCE INC.
    Inventors: Qingsong Liu, Jing Liu, Fengchao Lv, Chen Hu, Wen Liang Wang, Ao Li Wang, Zi Ping Qi, Xiao Fei Liang, Wen Chao Wang, Tao Ren, Bei Lei Wang, Li Wang
  • Publication number: 20200083591
    Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE, Chien-Hua CHEN
  • Publication number: 20200030596
    Abstract: A system for training visual acuity includes an audio player and a controller. The audio player includes a database which stores plural pieces of music, and a headphone with which a user listens to the pieces of music so as to stimulate a visual cortex of the user, where each of the pieces of music contains two audio frequency components that have a frequency difference therebetween ranging from 1 to 45 Hz. The controller is electrically connected to the audio player, and is configured to control the audio player to play the pieces of music.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 30, 2020
    Applicants: Eyeson Tech Ltd., Asia University
    Inventors: Shin-Da Lee, Chen-Chao Hsu, Hsin-Chin Chen, Chung-Hui Wang
  • Publication number: 20190367482
    Abstract: An inhibitor of a wild type and Y641 F mutant of human histone methyltransferase EZH2 is provided herein. Particularly, the inhibitor is a compound represented by formula (I) or a pharmaceutically acceptable salt thereof. The inhibitor can be used to treat a cancer or precancerous condition related to EZH2 activity.
    Type: Application
    Filed: January 17, 2018
    Publication date: December 5, 2019
    Applicant: TARAPEUTICS SCIENCE INC.
    Inventors: Qingsong LIU, Jing LIU, Fengchao LV, Chen HU, Wen Liang WANG, Ao Li WANG, Zi Ping Qi, Xiao Fei LIANG, Wen Chao WANG, Tao REN, Bei Lei WANG, Li WANG
  • Publication number: 20190329788
    Abstract: A road condition status prediction method is performed by a server and includes obtaining historical road segment information, the historical road segment information including road condition statuses and classification events that are used to classify the road condition statuses, and the classification events being determined based on content of the classification events, and obtaining an occurrence probability of each of the classification events, based on the obtained historical road segment information. The road condition status prediction method further includes obtaining a conditional probability of each of the classification events in each of the road condition statuses, based on the obtained historical road segment information, and predicting a road condition status of a road segment, based on the obtained occurrence probability of each of the classification events and the obtained conditional probability of each of the classification events in each of the road condition statuses.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Chen YUAN, Hong Chao Zhao, Bo Li, Zhi Jun Wang
  • Publication number: 20190214337
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Hsi CHOU, Tsun-Lung HSIEH, Chen-Chao WANG
  • Patent number: 10276382
    Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 30, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Publication number: 20190103386
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: William T. CHEN, John Richard HUNT, Chih-Pin HUNG, Chen-Chao WANG, Chih-Yi HUANG
  • Patent number: 10236240
    Abstract: In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • Patent number: 10186779
    Abstract: Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: January 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yu Ho, Chen-Chao Wang, Chun-Yen Ting, Ming-Fong Jhong, Po-Chih Pan
  • Patent number: 9968617
    Abstract: The present invention provides formulations and methods useful in the control of ectoparasites on a domestic animal, using a formulation comprising Indoxacarb and a veterinarily acceptable carrier that is applied topically to 10% or less of the total surface area of a domestic animal. Other embodiments include these formulations also including one or more additional pesticides such as fipronil.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 15, 2018
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Frank Guerino, Keith Alan Freehauf, Roger Mervyn Sargent, Peter Andrew O'Neill, Robert D. Simmons, Chen-Chao Wang
  • Publication number: 20180131094
    Abstract: Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 10, 2018
    Inventors: Cheng-Yu HO, Chen-Chao WANG, Chun-Yen TING, Ming-Fong JHONG, Po-Chih PAN
  • Publication number: 20180047571
    Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.
    Type: Application
    Filed: June 6, 2017
    Publication date: February 15, 2018
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Publication number: 20170330825
    Abstract: In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Hsi CHOU, Tsun-Lung HSIEH, Chen-Chao WANG
  • Patent number: 9728451
    Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 8, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Ying-Te Ou
  • Publication number: 20160008370
    Abstract: The present invention provides formulations and methods useful in the control of ectoparasites on a domestic animal, using a formulation comprising Indoxacarb and a veterinarily acceptable carrier that is applied topically to 10% or less of the total surface area of a domestic animal. Other embodiments include these formulations also including one or more additional pesticides such as fipronil.
    Type: Application
    Filed: September 23, 2015
    Publication date: January 14, 2016
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Frank GUERINO, Keith Alan Freehauf, Roger Mervyn Sargent, Peter Andrew O'Neil, Robert D. Simmons, Chen-Chao Wang
  • Publication number: 20140363967
    Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Inventors: Chen-Chao Wang, Ying-Te Ou
  • Patent number: 8841751
    Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 23, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chen-Chao Wang, Ying-Te Ou