Patents by Inventor Chen-Chao Wang
Chen-Chao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176305Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.Type: GrantFiled: February 18, 2022Date of Patent: December 24, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pao-Nan Lee, Chen-Chao Wang, Chang Chi Lee
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Patent number: 12132006Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.Type: GrantFiled: December 30, 2021Date of Patent: October 29, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pao-Nan Lee, Chen-Chao Wang, Chang Chi Lee
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Publication number: 20240230739Abstract: A measurement device and a method of measuring a radiation pattern by using the same are provided. The measurement device includes at least one positioner configured to move a first antenna for measuring a main lobe and a back lobe of an electromagnetic wave radiated from the first antenna.Type: ApplicationFiled: January 6, 2023Publication date: July 11, 2024Applicants: Advanced Semiconductor Engineering, Inc., National Chung Cheng UniversityInventors: Sheng-Chi HSIEH, Chen-Chao WANG, Sheng-Fuh CHANG, Chia-Chan CHANG, Shih-Cheng LIN, Yuan-Chun LIN, Wei-Lun HSU, Kuo-Hung CHENG
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Publication number: 20240186193Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: ApplicationFiled: February 12, 2024Publication date: June 6, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG
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Patent number: 11901245Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: GrantFiled: August 22, 2022Date of Patent: February 13, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Chih-Yi Huang, Keng-Tuan Chang
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Patent number: 11844199Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.Type: GrantFiled: January 26, 2022Date of Patent: December 12, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Chieh Hung, Chen-Chao Wang
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Publication number: 20230393194Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Publication number: 20230268293Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Patent number: 11733294Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: GrantFiled: March 6, 2020Date of Patent: August 22, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
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Publication number: 20230253302Abstract: An electronic package is disclosed. The electronic package includes an electronic component and a plurality of power regulating components. The plurality of power regulating components includes a first power regulating component and a second power regulating component. A first power path is established from the first power regulating component to a backside surface of the electronic component. A second power path is established from the second power regulating component to the backside surface of the electronic component.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Publication number: 20230240057Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Li-Chieh HUNG, Chen-Chao WANG
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Publication number: 20230215810Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Patent number: 11605877Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.Type: GrantFiled: August 19, 2019Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee, Chien-Hua Chen
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Publication number: 20230070369Abstract: A pharmaceutical composition of pyrazole compound and a surfactant and a method of using the same to treat atopic dermatitis.Type: ApplicationFiled: December 18, 2020Publication date: March 9, 2023Applicant: Intervet Inc.Inventors: Chad D. Brown, Christopher D. Kulczar, Chen-Chao Wang, Michelle H. Fung
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Publication number: 20220399240Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: ApplicationFiled: August 22, 2022Publication date: December 15, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG
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Patent number: 11515249Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.Type: GrantFiled: November 5, 2020Date of Patent: November 29, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Yi Huang, Chen-Chao Wang, Mi-Chun Hung
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Patent number: 11424167Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: GrantFiled: October 9, 2020Date of Patent: August 23, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Chih-Yi Huang, Keng-Tuan Chang
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Patent number: 11328999Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.Type: GrantFiled: December 6, 2019Date of Patent: May 10, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Fu-Chen Chu, Hung-Chun Kuo, Chen-Chao Wang
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Publication number: 20220139824Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Yi HUANG, Chen-Chao WANG, Mi-Chun HUNG
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Publication number: 20220115276Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.Type: ApplicationFiled: October 9, 2020Publication date: April 14, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Chih-Yi HUANG, Keng-Tuan CHANG