Abstract: An embedded memory control circuit is provided for use with a memory module consisting of a number of partly-defective memory chips to allow these partly-defective memory chips to be combined for use as a single memory unit with the same address space of each nondefective memory chip. The embedded memory control circuit includes a bank-select unit, a bank-suppress unit, and a data output buffer. The bank-select unit is capable of detecting whether each of the banks in the memory module is defective or nondefective to thereby generate a plurality of corresponding bank-status signals each indicative of whether the corresponding bank is defective or nondefective. The bank-suppress unit is capable of, in response to the bank-status signals and the bank-select signal, generating a plurality of defective-bank suppressing signals which can suppress each defective bank in the memory module, if any.