Abstract: A method for testing a ball grid array package includes the following steps. Firstly, a printed circuit board having a plurality of contact pads thereon is provided. Then, a ball grid array test socket assembly having a connecting interface, a plurality of resilient contact members and a plurality of conducting members penetrating through the connecting interface is provided. The first terminal of each conducting member is in contact with the second terminal of corresponding resilient contact member. The second terminal of each conducting member is in contact with corresponding contact pad on the printed circuit board. Afterwards, the ball contacts of the ball grid array package are in contact with corresponding first terminals of the resilient contact members so as to test the ball grid array package.

Abstract: An expanding error correction architecture groups the output data of a data end to several parts, and each grouped output data of the data end is connected to one of a plurality of error correction circuit to be processed for a check sum. One part of the output data of the data end is arranged in a successive form, and another part of the output data of the data end is arrange in a non-successive form. The architecture of the present invention increases the error detection ability for check sums of different data sizes in the data end.

Abstract: A data reading structure for a 8-bit microprocessor to read several bytes of data at a time has a memory module and a selector module. The memory module has a first memory having a first and second data output ports and a second memory has a third and fourth data output ports. The selector module has a first data selector, a second data selector and a third data selector. The first, second and third data selectors respectively select one output from the first, second, third and fourth data output ports. Thereby, the microprocessor is allowed to read successively three bytes of data from an output terminal of the selector module during a memory read cycle to reduce the fetch time of an instruction.

Abstract: A memory circuit is designed for a Universal Serial Bus (USB) 2.0 circuit architecture. An analog front end unit is connected to a high-speed delay phase lock loop unit. A full-speed delay phase lock loop and data recovery unit is connected to the analog front end unit. A receiver unit is connected to the high-speed delay phase lock loop unit and the full-speed delay phase lock loop and data recovery unit. A transceiver unit is connected to the analog front end unit and the receiver unit. A control unit is connected to the transceiver unit, the receiver unit, the high-speed delay phase lock loop unit and the full-speed delay phase lock loop and data recovery unit. An external oscillator unit is connected to the control unit.

Abstract: A buffer controller between a first and a second memories is used to control the buffer during data transmission process for memories. The buffer controller between memories has a microprocessor used to process the data transmission of the memory bus, a first memory connected to the microprocessor, and a second memory also connected to the microprocessor. The first memory and the second memory therefore transmit data under the control of the microprocessor.