Patents by Inventor Chen Chiang Yu

Chen Chiang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096035
    Abstract: A composite wafer may be provided by: forming a layer stack including a carrier layer, an ion implantation layer, and a transfer material layer by implanting ions into a donor wafer; forming intersecting trenches through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer; attaching the layer stack to an acceptor wafer including a stack of a handle substrate and a first dielectric oxide layer by bonding the layer stack to the first dielectric oxide layer; and cleaving the layer stack at the ion implantation layer, whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventors: Chen-Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250053064
    Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Su-Chun Yang, Chen Chiang Yu, Jui Hsuan Tsai, Jih-Churng Twu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240128217
    Abstract: A semiconductor device includes a first semiconductor die and a second semiconductor die connected to the first semiconductor die. Each of the first semiconductor die and the second semiconductor die includes a substrate, a conductive bump formed on the substrate and a conductive contact formed on the conductive bump. The conductive contact has an outer lateral sidewall, there is an inner acute angle included between the outer lateral sidewall and the substrate is smaller than 85°, and the conductive contact of the first semiconductor die is connected opposite to the conductive contact of the second semiconductor die.
    Type: Application
    Filed: January 20, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung CHEN, Chen Chiang YU, Wei-An TSAO, Tsung-Fu TSAI, Szu-Wei LU, Chung-Shi LIU
  • Publication number: 20240006268
    Abstract: A package structure includes a circuit substrate, a semiconductor device, a plurality of cooling pins, a cooler lid, an anti-fouling coating and a top lid. The semiconductor device is disposed on and electrically connected to the circuit substrate. The cooling pins are disposed on the semiconductor device. The cooler lid is attached to the cooling pins, wherein the cooler lid includes an inlet opening and an outlet opening exposing portions of the cooling pins. The anti-fouling coating is coated on the cooling pins and on an inner surface of the cooler lid. The top lid is attached to an outer surface of the cooler lid.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu
  • Publication number: 20230402345
    Abstract: A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Chen Chiang Yu, Tsung-Fu Tsai, Szu-Wei Lu