Abstract: A laptop computer with a quick-release keyboard including a host, a display, and a keyboard is provided. The host has a first surface and a second surface opposite to each other. The host has at least one movable hook disposed on the first surface. The display is pivoted to the host to be folded or unfolded relative to the first surface of the host. The laptop computer is supported on a platform via the second surface when the display is unfolded relative to the first surface of the host. The keyboard has a locking column to be locked by the movable hook when the keyboard is disposed on the first surface, such that the keyboard is fixed on the first surface.

Abstract: The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows.

Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The gate is embedded in the gate dielectric layer. The transistor structure density can be improved.

Abstract: The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and a second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer, a third isolation layer on the first the second isolation layers, a bit line via contact through the first and the third isolation layers, and a conductive layer on the bit line via contact and the third isolation layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers.

Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.

Abstract: The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged.

Abstract: The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer embedded in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers, and the concave portion is defined as a main body. The main body includes a bulk region. The gate conductive layer facing toward the concave portion serves as a gate.

Abstract: A method of forming a memory device including forming a stack of silicon nitride layers and polysilicon layers that are alternating arranged, etching a serpentine trench in the stack of silicon nitride layers and polysilicon layers, forming a first isolation layer in the serpentine trench, removing one of the silicon nitride layers to form a recess between neighboring two of the polysilicon layers, and forming in sequence a doped polysilicon layer, a gate dielectric layer, and a conductive layer in the recess.

Abstract: The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows.

Abstract: The invention discloses a NOR-type memory device and a method of fabricating such NOR-type memory device. The NOR-type memory device according to a preferred embodiment of the invention includes a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of multi-layer stripes, a plurality of memory cells, a plurality of first sub-bit lines, a plurality of second sub-bit line, a plurality of word lines, an insulating layer, a plurality of grounded via contacts, and a grounding layer. The first isolation stripes and the second isolation stripes extend in a longitudinal direction defined by the semiconductor substrate. Each memory cell corresponds to one of the columns and one of the rows defined by the semiconductor substrate. The memory cells on one side of each first isolation stripe and the memory cells on the other side of said one first isolation stripe are staggeredly arranged.

Abstract: The disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first and a second polysilicon layers on the substrate, a third polysilicon layer between the first and the second polysilicon layers, a first isolation layer adjacent with the first to the third polysilicon layers, a gate dielectric layer and a gate conductive layer in the third polysilicon layer, a second isolation layer on the gate conductive layer and the third polysilicon layer, a third isolation layer on the first the second isolation layers, a bit line via contact through the first and the third isolation layers, and a conductive layer on the bit line via contact and the third isolation layer. The third polysilicon layer has a concave portion between the first and the second polysilicon layers.

Abstract: The invention discloses a transistor, a three dimensional memory device including such transistors and a method of fabricating such memory device. The transistor according to the invention includes a pillar of a semiconductor material, extending in a normal direction of a semiconductor substrate, a gate dielectric layer and a gate conductor. The pillar of the semiconductor material has a base side face parallel to the normal direction, a tapered side face opposite to the base side face, a top face perpendicular to the normal direction, a bottom face opposite to the top face, a front side face adjacent to the base side face and the tapered side face, and a rear side face opposite to the front side face. A first elongated portion, sandwiched among the base side face, the front side face, the bottom face and the top face, forms a source region. A second elongated portion, sandwiched among the base side face, the rear side face, the bottom face and the top face, forms a drain region.

Abstract: A method of forming a memory device including forming a stack of silicon nitride layers and polysilicon layers that are alternating arranged, etching a serpentine trench in the stack of silicon nitride layers and polysilicon layers, forming a first isolation layer in the serpentine trench, removing one of the silicon nitride layers to form a recess between neighboring two of the polysilicon layers, and forming in sequence a doped polysilicon layer, a gate dielectric layer, and a conductive layer in the recess.

Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The gate is embedded in the gate dielectric layer. The transistor structure density can be improved.

Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.

Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.