Patents by Inventor Chen-Chih Wu

Chen-Chih Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Guard ring structure of semiconductor arrangement
    Patent number: 11081363
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Targeted prodrug cytosine deaminase fusion carrier and application thereof
    Patent number: 10947270
    Abstract: The present invention provides a targeted prodrug enzyme fusion carrier comprising a targeted molecule and a prodrug enzyme. The targeted prodrug enzyme fusion carrier can effectively identify and bind to tumor cells and tumor-induced tumor angiogenesis. The targeted prodrug enzyme fusion carrier also has a targeted prodrug enzyme fusion protein and a theranostic system utilizing the method of in vivo nuclear medicine for the clinical diagnosis and treatment of individual patients with tumors.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: March 16, 2021
    Assignee: NATIONAL YANG-MING UNIVERSITY
    Inventors: C. Allen Chang, Hsin-Ell Wang, Jia-Je Li, Shun-Fu Chang, Roy Chen-Chih Wu
  • GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
    Publication number: 20200118834
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Guard ring structure of semiconductor arrangement
    Patent number: 10510554
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • TARGETED PRODRUG ENZYME FUSION CARRIER AND APPLICATION THEREOF
    Publication number: 20190211057
    Abstract: The present invention provides a targeted prodrug enzyme fusion carrier comprising a targeted molecule and a prodrug enzyme. The targeted prodrug enzyme fusion carrier can effectively identify and bind to tumor cells and tumor-induced tumor angiogenesis. The targeted prodrug enzyme fusion carrier also has a targeted prodrug enzyme fusion protein and a theranostic system utilizing the method of in vivo nuclear medicine for the clinical diagnosis and treatment of individual patients with tumors.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 11, 2019
    Inventors: C. Allen Chang, Hsin-Ell Wang, Jia-Je Li, Shun-Fu Chang, Roy Chen-Chih Wu
  • GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
    Publication number: 20190109014
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Guard ring structure of semiconductor arrangement
    Patent number: 10170333
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
    Publication number: 20180233377
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
  • Guard ring structure of semiconductor arrangement
    Patent number: 9941141
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
    Publication number: 20170194165
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
  • Guard ring structure of semiconductor arrangement
    Patent number: 9601625
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT
    Publication number: 20150021713
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Application
    Filed: July 14, 2014
    Publication date: January 22, 2015
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • Resistors formed based on metal-oxide-semiconductor structures
    Patent number: 8648425
    Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Han Wang, Chen-Chih Wu, Sheng-Fang Cheng, Kuo-Ji Chen
  • Resistors Formed Based on Metal-Oxide-Semiconductor Structures
    Publication number: 20130001704
    Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.
    Inventors: Wen-Han Wang, Chen-Chih Wu, Sheng-Fang Cheng, Kuo-Ji Chen