Patents by Inventor Chen-Chih Wu
Chen-Chih Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961800Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.Type: GrantFiled: July 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
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Publication number: 20240090230Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.Type: ApplicationFiled: January 9, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20240072156Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate, semiconductor channel sheets disposed over the semiconductor substrate, and source and drain regions located beside the semiconductor channel sheets. A gate structure is disposed between the source and drain regions and disposed over the semiconductor channel sheets. The gate structure laterally surrounds the semiconductor channel sheets. The gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets. Sidewall spacers are disposed between the gate structure and source and drain regions, and the sidewall spacers located next to the top gate electrode structure have slant sidewalls.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen, Hsuan-Chih Wu
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Patent number: 11081363Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: GrantFiled: December 13, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
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Patent number: 10947270Abstract: The present invention provides a targeted prodrug enzyme fusion carrier comprising a targeted molecule and a prodrug enzyme. The targeted prodrug enzyme fusion carrier can effectively identify and bind to tumor cells and tumor-induced tumor angiogenesis. The targeted prodrug enzyme fusion carrier also has a targeted prodrug enzyme fusion protein and a theranostic system utilizing the method of in vivo nuclear medicine for the clinical diagnosis and treatment of individual patients with tumors.Type: GrantFiled: January 14, 2019Date of Patent: March 16, 2021Assignee: NATIONAL YANG-MING UNIVERSITYInventors: C. Allen Chang, Hsin-Ell Wang, Jia-Je Li, Shun-Fu Chang, Roy Chen-Chih Wu
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Publication number: 20200118834Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
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Patent number: 10510554Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: GrantFiled: November 30, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
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Publication number: 20190211057Abstract: The present invention provides a targeted prodrug enzyme fusion carrier comprising a targeted molecule and a prodrug enzyme. The targeted prodrug enzyme fusion carrier can effectively identify and bind to tumor cells and tumor-induced tumor angiogenesis. The targeted prodrug enzyme fusion carrier also has a targeted prodrug enzyme fusion protein and a theranostic system utilizing the method of in vivo nuclear medicine for the clinical diagnosis and treatment of individual patients with tumors.Type: ApplicationFiled: January 14, 2019Publication date: July 11, 2019Inventors: C. Allen Chang, Hsin-Ell Wang, Jia-Je Li, Shun-Fu Chang, Roy Chen-Chih Wu
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Publication number: 20190109014Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
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Patent number: 10170333Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: GrantFiled: April 9, 2018Date of Patent: January 1, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
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Publication number: 20180233377Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: ApplicationFiled: April 9, 2018Publication date: August 16, 2018Inventors: Sheng-Fang CHENG, Chen - Chih WU, Chien-Yuan LEE, Yen-Lin LIU
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Patent number: 9941141Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: GrantFiled: March 20, 2017Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
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Publication number: 20170194165Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: ApplicationFiled: March 20, 2017Publication date: July 6, 2017Inventors: Sheng-Fang Cheng, Chen-Chih Wu, Chien-Yuan Lee, Yen-Lin Liu
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Patent number: 9601625Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: GrantFiled: July 14, 2014Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
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Publication number: 20150021713Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.Type: ApplicationFiled: July 14, 2014Publication date: January 22, 2015Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
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Patent number: 8648425Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.Type: GrantFiled: June 28, 2011Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Han Wang, Chen-Chih Wu, Sheng-Fang Cheng, Kuo-Ji Chen
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Publication number: 20130001704Abstract: A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.Inventors: Wen-Han Wang, Chen-Chih Wu, Sheng-Fang Cheng, Kuo-Ji Chen