Patents by Inventor Chen Chin
Chen Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978472Abstract: A system for processing and presenting a conversation includes a sensor, a processor, and a presenter. The sensor is configured to capture an audio-form conversation. The processor is configured to automatically transform the audio-form conversation into a transformed conversation. The transformed conversation includes a synchronized text, wherein the synchronized text is synchronized with the audio-form conversation. The presenter is configured to present the transformed conversation including the synchronized text and the audio-form conversation. The presenter is further configured to present the transformed conversation to be navigable, searchable, assignable, editable, and shareable.Type: GrantFiled: March 23, 2021Date of Patent: May 7, 2024Assignee: Otter.ai, Inc.Inventors: Yun Fu, Simon Lau, Kaisuke Nakajima, Julius Cheng, Gelei Chen, Sam Song Liang, James Mason Altreuter, Kean Kheong Chin, Zhenhao Ge, Hitesh Anand Gupta, Xiaoke Huang, James Francis McAteer, Brian Francis Williams, Tao Xing
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Publication number: 20240147718Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate including a logic region and a memory cell region. A logic device is arranged on the logic region. A memory device is arranged on the memory cell region. An isolation structure extends into a top surface of the semiconductor substrate, and laterally separates the logic region from the memory cell region. The isolation structure includes dielectric material and has an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to memory cell region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11974311Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.Type: GrantFiled: March 1, 2023Date of Patent: April 30, 2024Assignee: Hannibal IP LLCInventors: Wan-Chen Lin, Yu-Hsin Cheng, Heng-Li Chin, Hsin-Hsi Tsai
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Publication number: 20240097216Abstract: The present invention discloses a detection device and a probe module thereof, wherein an electrical connection path between a battery detection frame and a battery under test is provided via the probe module. The probe module includes a base, a first polarity plate, a second polarity plate, a first upper connection group, a second upper connection group, a first lower connection member and a second lower connection member. Via the first polarity plate, the first upper connection group is correspondingly coupled to the battery detection frame, and the first lower connection member is correspondingly coupled to the battery under test. Via the second polarity plate, the second upper connection group is correspondingly coupled to the battery detection frame, and the second lower connection member is correspondingly coupled to the battery under test. Thus, it is not necessary to process a cable having been fixed on the battery detection frame when the probe module is replaced.Type: ApplicationFiled: June 8, 2023Publication date: March 21, 2024Inventors: CHUAN-TSE LIN, CHEN-CHOU WEN, SHIH-CHIN TAN, WEN-CHUAN CHANG, YING-CHENG CHEN
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Patent number: 11895836Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.Type: GrantFiled: September 16, 2020Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Publication number: 20220359552Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 11430799Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: September 30, 2019Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Patent number: 11264292Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: November 13, 2019Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11195834Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.Type: GrantFiled: May 4, 2020Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
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Patent number: 11088040Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: September 21, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang
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Patent number: 11031294Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.Type: GrantFiled: August 13, 2018Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
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Publication number: 20200411534Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.Type: ApplicationFiled: September 16, 2020Publication date: December 31, 2020Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Publication number: 20200393511Abstract: An IC testing apparatus whereby a wedge body with inclined surfaces is attached to a bottom side of existing contact finger modules. The inclined support is then attached to the top of a load board of the testing apparatus. The inclined surfaces cause the normally horizontal finger modules to become inclined to the horizontal. In this manner, testing can be carried out in the usual way with existing contact finger modules, whilst the problems of IC device contact pad burr and oxidization are solved. Furthermore, because the outer, load board end of the contact fingers are also at an angle, these outer tips of the contact fingers naturally come into contact with the load board, without requiring any soldering.Type: ApplicationFiled: June 11, 2020Publication date: December 17, 2020Applicant: JF MICROTECHNOLOGY SDN. BHD.Inventors: Wei Kuong FOONG, Kok Sing GOH, Shamal MUNDIYATH, Eng Kiat LEE, Muhamad Izzat bin ROSLEE, Mei Chen CHIN
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Publication number: 20200373317Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 10804281Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.Type: GrantFiled: October 24, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu, Chih-Pin Huang
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Publication number: 20200266196Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: Meng-Han LIN, Chih-Ren HSIEH, Chen-Chin LIU
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Patent number: 10741569Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Patent number: 10672778Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Patent number: 10644000Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.Type: GrantFiled: November 19, 2018Date of Patent: May 5, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chen-Chin Liu
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Patent number: D959531Type: GrantFiled: December 10, 2020Date of Patent: August 2, 2022Assignee: CHAINSEM TECHNOLOGY CORPORATIONInventor: Chen-Chin Chiu