Abstract: A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.

Abstract: A method of forming a self-aligned contact on a device including a semiconductor substrate comprises the steps of forming a gate oxide layer on the substrate, forming a gate electrode layer on the gate oxide layer, forming a stacked dielectric structure stacked on the gate electrode layer, and then patterning the stacked dielectric structure and the gate electrode layer, forming a dielectric layer blanketing the device, forming a first mask over the dielectric layer, the first mask covering a masked region, and then etching the dielectric layer through the mask to form a self-aligned contact opening into the dielectric layer leaving a first dielectric spacer adjacent to the stacked gate electrode and leaving the masked region covered by the remainder of the dielectric layer, removing the first mask, deposition of a second electrode layer, then forming a second mask and patterning the electrode layer by etching through the second mask, thereby forming a self-aligned contact structure in the opening.

Abstract: A symmetrical, SRAM silicon device comprises substrate comprising a semiconductor material with, a set of buried local interconnection lines in the silicon substrate. A word line is located centrally on the surface of the device. Pull down transistors are located symmetrically one either side of the word line. Interconnections are formed in the same layer as a BN+ diffusion. There is only one wordline composed of polysilicon. The pull down transistors are located on opposite sides of the word line. The cell size is small. There is no 45.degree. layout, and the metal rule is loose. Pass transistor source and drain regions are in the substrate juxtaposed with the buried local interconnection line. There is a layer of gate oxide above the source region and the drain region, and a gate adore the gate oxide juxtaposed with the source region and drain region.