Patents by Inventor Chen-Chou Huang
Chen-Chou Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230393873Abstract: A value-added content providing method for a computer system includes receiving an input message indicating to present a pop-up window in a display area of the computer system; obtaining a content area in the display area according to the input message; analyzing the content area to generate an analysis content; and providing and displaying a value-added content in the pop-up window according to the analysis content.Type: ApplicationFiled: June 4, 2023Publication date: December 7, 2023Applicants: Inventec (Pudong) Technology Corp., Inventec CorporationInventors: Hsueh-Liang Chen, Chen-Chou Huang, Yan-Yue Yin
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Publication number: 20190146634Abstract: An adjusting method of a virtual keyboard adapted to a first touch device is disclosed. The first touch device displays a virtual keyboard with several keys. The adjusting method includes the following operations: adjusting a position and a size of the virtual keyboard displayed on the first touch device according to an operating range of a user; collecting several first click points on the virtual keyboard and one of the keys corresponding to the first click points; analyzing several press distributions of the keys according to the first click points; determining one of the keys corresponding to a second click point according to the press distributions and center points of the keys; transmitting the press distributions and the position and the size of the virtual keyboard to a server; and transmitting the press distributions and the position and the size of the virtual keyboard to a second touch device.Type: ApplicationFiled: December 24, 2017Publication date: May 16, 2019Inventor: Chen-Chou Huang
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Patent number: 10282037Abstract: An adjusting method of a virtual keyboard adapted to a first touch device is disclosed. The first touch device displays a virtual keyboard with several keys. The adjusting method includes the following operations: adjusting a position and a size of the virtual keyboard displayed on the first touch device according to an operating range of a user; collecting several first click points on the virtual keyboard and one of the keys corresponding to the first click points; analyzing several press distributions of the keys according to the first click points; determining one of the keys corresponding to a second click point according to the press distributions and center points of the keys; transmitting the press distributions and the position and the size of the virtual keyboard to a server; and transmitting the press distributions and the position and the size of the virtual keyboard to a second touch device.Type: GrantFiled: December 24, 2017Date of Patent: May 7, 2019Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventor: Chen-Chou Huang
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Publication number: 20120132790Abstract: An electronic device having proximity detection function includes a front cover, a frame arranged under the front cover, a light emitter and a photo sensor received in the frame. A spacer is arranged between the front cover and the frame to prevent a portion of light from the light emitter from travelling to the photo sensor, when the front cover and the frame are not parallel.Type: ApplicationFiled: April 28, 2011Publication date: May 31, 2012Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHEN-CHOU HUANG, CHUN-YU LEE
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Patent number: 7074700Abstract: A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.Type: GrantFiled: September 17, 2004Date of Patent: July 11, 2006Assignee: Nanya Technology CorporationInventors: Cheng-Chih Huang, Sheng-Wei Yang, Chen-Chou Huang, Sheng-Tsung Chen
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Patent number: 6962847Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.Type: GrantFiled: May 14, 2004Date of Patent: November 8, 2005Assignee: Nanya Technology CorporationInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Patent number: 6958283Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.Type: GrantFiled: October 22, 2003Date of Patent: October 25, 2005Assignee: Nanya Technology CorporationInventors: Chien-Mao Liao, Tzu-En Ho, Chang-Rong Wu, Chih-How Chang, Sheng-Wei Yang, Sheng-Tsung Chen, Chung-Yuan Lee, Wen-Sheng Liao, Chen-Chou Huang
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Patent number: 6927123Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.Type: GrantFiled: May 14, 2004Date of Patent: August 9, 2005Assignee: Nanya Technology CorporationInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Publication number: 20050124111Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.Type: ApplicationFiled: May 14, 2004Publication date: June 9, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Publication number: 20050124110Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined dept, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.Type: ApplicationFiled: May 14, 2004Publication date: June 9, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Cheng-Chih Huang, Sheng-Wei Yang, Neng-Tai Shih, Chen-Chou Huang
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Publication number: 20050064643Abstract: A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.Type: ApplicationFiled: September 17, 2004Publication date: March 24, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Cheng-Chih Huang, Sheng-Wei Yang, Chen-Chou Huang, Sheng-Tsung Chen
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Publication number: 20050020028Abstract: A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.Type: ApplicationFiled: October 22, 2003Publication date: January 27, 2005Inventors: Chien-Mao Liao, Tzu-En Ho, Chang-Rong Wu, Chih-How Chang, Sheng-Wei Yang, Sheng-Tsung Chen, Chung-Yuan Lee, Wen-Sheng Liao, Chen-Chou Huang
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Patent number: 6835641Abstract: A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A single sided silicon layer adjacent to the sidewall in the opening. The single sided silicon layer exposes a portion of the opening base surface. The single sided silicon layer is implanted with fluorine-containing ions. The substrate and the single sided silicon layer is thermally oxidized to form a thermal oxide layer in the opening.Type: GrantFiled: April 30, 2004Date of Patent: December 28, 2004Assignee: Nanya Technology CorporationInventors: Sweehan J. H. Yang, Chen-Chou Huang
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Publication number: 20040175877Abstract: A method of forming a bottle-shaped trench. A trench is formed in a substrate, wherein the trench has a surface with an upper portion and a lower portion beneath the upper portion. A dielectric layer is formed on the trench surface at the lower portion. Using the dielectric layer as a mask, a nitridation procedure is performed to form a nitride film on the trench surface at the upper portion. The dielectric layer is removed. Using the nitride film as a mask, an isotropic etching procedure is performed to form a space in the trench at the lower portion. Thus, a bottle-shaped trench is formed.Type: ApplicationFiled: February 20, 2004Publication date: September 9, 2004Inventors: Shian-Jyh Lin, Chen-Chou Huang, Ming-Cheng Chang, Hsien-Hao Liao, Meng-Hung Chen