Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.

Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Abstract: A pixel unit includes a gate line, a first data line, a second data line, a first active device, and a pixel electrode. The first active device is electrically connected to the gate line and the first or second data line. The pixel electrode is electrically connected to the first active device. The pixel electrode includes a first sub-pixel electrode, a second sub-pixel electrode, and a first connecting electrode. Each of the first sub-pixel electrode and the second sub-pixel electrode includes a trunk electrode, a traverse trunk electrode, and branch electrodes. The first connecting electrode connects the first sub-pixel electrode to the second sub-pixel electrode.

Abstract: A liquid crystal display panel includes first substrate, active switching device, patterned insulating layer, pixel electrode, auxiliary electrode, second substrate, common electrode and liquid crystal molecules. The patterned insulating layer is disposed on the first substrate and includes a plurality of inner insulating branches and slits, and each slit is located between two adjacent inner insulating branches. The pixel electrode is disposed on the patterned insulating layer and electrically connected to the active switching device. The periphery of the pixel electrode overlaps the inner insulating branches. The auxiliary electrode is disposed on the first substrate and at least partially surrounding the pixel electrode. The auxiliary electrode and the pixel electrode are not electrically connected, and the inner insulating branches partially overlap the auxiliary electrode in a vertical projection direction. The common electrode is disposed on the second substrate.

Abstract: A display panel includes a pixel electrode and a common electrode. The pixel electrode has a cross-shaped opening which includes a first slit extending along a first direction and a second slit extending along a second direction and crossing the first slit. The common electrode is at least disposed at one side of the pixel electrode. The common electrode includes an opening having a largest width in the first direction, and a part of the opening with the largest width is adjacent to an intersection of an extending direction of the first slit and the common electrode. A width of the opening is gradually smaller from the part of the opening with the largest width along the second direction and an opposite direction of the second direction.

Abstract: A pixel unit includes a gate line, a first data line, a second data line, a first active device, and a pixel electrode. The first active device is electrically connected to the gate line and the first or second data line. The pixel electrode is electrically connected to the first active device. The pixel electrode includes a first sub-pixel electrode, a second sub-pixel electrode, and a first connecting electrode. Each of the first sub-pixel electrode and the second sub-pixel electrode includes a trunk electrode, a traverse trunk electrode, and branch electrodes. The first connecting electrode connects the first sub-pixel electrode to the second sub-pixel electrode.

Abstract: A display panel includes a pixel electrode and a common electrode. The pixel electrode has a cross-shaped opening which includes a first slit extending along a first direction and a second slit extending along a second direction and crossing the first slit. The common electrode is at least disposed at one side of the pixel electrode. The common electrode includes an opening having a largest width in the first direction, and a part of the opening with the largest width is adjacent to an intersection of an extending direction of the first slit and the common electrode. A width of the opening is gradually smaller from the part of the opening with the largest width along the second direction and an opposite direction of the second direction.

Abstract: A display panel includes pixel structures. Each pixel structure includes an active device, a pixel electrode, and a protective layer. The pixel electrode is electrically connected to the active device, wherein the pixel electrode has at least one block-shaped electrode. The protective layer is located below the pixel electrode and includes a recess main portion and recess branched portions. The width of the recess main portion is greater than 0 ?m and equal to or less than 4 ?m, and the recess branched portions are extended along at least four directions. The pixel electrode covers the recess main portion and the recess branched portions. The display panel includes at least one polarizer, wherein the direction of an adsorption axis of the polarizer is different from the four directions of extension of the recess branched portions.

Abstract: A display panel including a first substrate, a pixel array disposed on the first substrate, a first alignment layer covering the pixel array, a second substrate disposed opposite the first substrate, a second alignment layer disposed on the second substrate and a display medium disposed between the first alignment layer and the second alignment layer is provided. The first alignment layer has first alignment particles. A number of the first alignment particles each having an area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the first alignment particles in a unit area. The second alignment layer has second alignment particles. A number of the second alignment particles each having the area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the second particles in the unit area.

Abstract: A display panel includes pixel structures. Each pixel structure includes an active device, a pixel electrode, and a protective layer. The pixel electrode is electrically connected to the active device, wherein the pixel electrode has at least one block-shaped electrode. The protective layer is located below the pixel electrode and includes a recess main portion and recess branched portions. The width of the recess main portion is greater than 0 ?m and equal to or less than 4 ?m, and the recess branched portions are extended along at least four directions. The pixel electrode covers the recess main portion and the recess branched portions. The display panel includes at least one polarizer, wherein the direction of an adsorption axis of the polarizer is different from the four directions of extension of the recess branched portions.

Abstract: A liquid crystal display panel includes a first substrate, a conductive line, an active switch device, a pixel electrode and a first electrode. The pixel electrode has a cruciform opening, which includes a first slit extending along a first direction and a second slit extending along a second direction intersecting the first slit. The first electrode is disposed on the first substrate and located adjacent to the periphery of the pixel electrode. The pixel electrode includes two first parts and a second part, where the two first parts are respectively disposed adjacent to two opposite ends of the second slit in the second direction. The distance between the two first parts in the second direction has a first width, the second part has a second width in the second direction, and the first width is greater than the second width.

Abstract: A liquid crystal display panel includes first substrate, active switching device, patterned insulating layer, pixel electrode, auxiliary electrode, second substrate, common electrode and liquid crystal molecules. The patterned insulating layer is disposed on the first substrate and includes a plurality of inner insulating branches and slits, and each slit is located between two adjacent inner insulating branches. The pixel electrode is disposed on the patterned insulating layer and electrically connected to the active switching device. The periphery of the pixel electrode overlaps the inner insulating branches. The auxiliary electrode is disposed on the first substrate and at least partially surrounding the pixel electrode. The auxiliary electrode and the pixel electrode are not electrically connected, and the inner insulating branches partially overlap the auxiliary electrode in a vertical projection direction. The common electrode is disposed on the second substrate.

Abstract: A display panel including a first substrate, a pixel array disposed on the first substrate, a first alignment layer covering the pixel array, a second substrate disposed opposite the first substrate, a second alignment layer disposed on the second substrate and a display medium disposed between the first alignment layer and the second alignment layer is provided. The first alignment layer has first alignment particles. A number of the first alignment particles each having an area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the first alignment particles in a unit area. The second alignment layer has second alignment particles. A number of the second alignment particles each having the area ranged from 250 nm2 to 1000 nm2 occupies 40% or less of a total number of the second particles in the unit area.

Abstract: A tri-state liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The first substrate and the second substrate are disposed oppositely. The liquid crystal layer disposed between the first substrate and the second substrate includes a plurality of polymer network liquid crystals. The first electrode is disposed between the first substrate and the liquid crystal layer, the second electrode is disposed between the second substrate and the liquid crystal layer, and the first and second electrodes include planar electrodes. The third and fourth electrodes are disposed between the first substrate and the liquid crystal layer, and the third and fourth electrodes include patterned electrodes. The tri-state liquid crystal display panel has a transmission state display mode, a dark state display mode and a haze state display mode.

Abstract: A tri-state liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The first substrate and the second substrate are disposed oppositely. The liquid crystal layer disposed between the first substrate and the second substrate includes a plurality of polymer network liquid crystals. The first electrode is disposed between the first substrate and the liquid crystal layer, the second electrode is disposed between the second substrate and the liquid crystal layer, and the first and second electrodes include planar electrodes. The third and fourth electrodes are disposed between the first substrate and the liquid crystal layer, and the third and fourth electrodes include patterned electrodes. The tri-state liquid crystal display panel has a transmission state display mode, a dark state display mode and a haze state display mode.

Abstract: A fabricating method of field emission triodes is provided. First, a cathode conductive layer, an insulator layer, and a gate layer are formed on a substrate. An opening is formed in the insulator layer and the gate layer to expose a portion of the cathode conductive layer. A metal layer is formed on the cathode conductive layer. A first anodization is performed so as to form a first metal anodization layer from a portion of the metal layer. After the first metal anodization layer is removed, a second metal anodization layer having a plurality of pores is formed. Thereafter, a catalyst layer is formed in the pores. Then, a plurality of carbon nanotubes are formed in the pores.

Abstract: A fabricating method of a field emission device array substrate is provided, which includes the following steps. First, a substrate is provided. Then, a cathode conductive layer is formed on the substrate. Moreover, an anodized layer with a plurality of holes is formed on the cathode conductive layer. Thereafter, a plurality of electron emitters is formed within the holes respectively. Additionally, an insulation layer is formed to cover the electron emitters and the anodized layer. Then, a gate material layer is formed on the insulation layer. Thereafter, the gate material layer is patterned to form a gate layer. The gate layer and the insulation layer have an opening to expose the electron emitters.

Abstract: A fabricating method of field emission triodes is provided. First, a cathode conductive layer, an insulator layer, and a gate layer are formed on a substrate. An opening is formed in the insulator layer and the gate layer to expose a portion of the cathode conductive layer. A metal layer is formed on the cathode conductive layer. A first anodization is performed so as to form a first metal anodization layer from a portion of the metal layer. After the first metal anodization layer is removed, a second metal anodization layer having a plurality of pores is formed. Thereafter, a catalyst layer is formed in the pores. Then, a plurality of carbon nanotubes are formed in the pores.