Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing a first conductive material layer over a substrate, patterning the first conductive material layer to form a first conductor plate over the substrate, forming a first high-K dielectric layer over the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, where a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer.

Abstract: A method for treating fluoride-containing waste water is disclosed. The method includes, first, inducing fluoride-containing waste water and calcium compound into a crystallization reaction tank having a plurality of crystallizing webs so as to conduct a reaction between the fluoride-containing waste water and the calcium compound to form calcium fluoride crystals on the crystallizing webs; meanwhile, stirring the fluoride-containing waste water and the; then, discharging the fluoride-containing waste water out of the crystallization reaction tank for conducting a successive treating step.

Abstract: A bearing assembly with auxiliary magnetism comprises a shaft, a fan base and a bearing. The fan base provides a hollow shaft seat with a receiving space to accommodate the shaft. The bearing fits with the shaft for supporting the shaft. A magnetic part surrounds the shaft to attract the shaft such that the fan blade hub can be fixed at a specific position.

Abstract: A system of sludge dewatering is described. The system comprises of a filter press, a sludge fee pipe, and acid feed pipe, and exhaust pipe and a discharge pipe. The sludge feed pipe is configured on the filter press. The acid feed pipe is connected with the sludge feed pipe. The exhaust pipe is connected with the sludge feed pipe. The discharge pipe is configured on the filter press. The system of the present invention can lead the acid solution into the filter press by the acid feed pipe so as to use in situ way to proceed filter cloth washing of the filter press.

Abstract: A drained water recovery system of a process device and recovering method thereof is provided. The recovering method includes using a conductivity meter to measure the conductivity of the drained water so that the drained water with different degrees of conductivity are channeled to different pipelines. Furthermore, another conductivity meter and a total organic carbon analyzer together with an interim tank liquid level controller sorts out the recovered water. Thereafter, according to the properties of the recovered water, the drained water is re-used to improve recycling efficiency.

Abstract: The present invention relates to a watch holder system, which is worn on the back side of a hand, comprising a casing, an elastic cord, and a buckle. The casing is provided with two holes passing through from the front end to the back end and accommodating the elastic cord. The lower side of the casing is concave to match the surface of the back side of the hand. By the wearing position of the watch holder system, a novel and beautiful effect is created. In use, the watch will not be covered by a long sleeve, thus allowing for unhindered reading of the displayed time.