Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: The present invention discloses a dielectric filter with multilayer resonator, including a dielectric block, a plurality of multilayer resonator formed in the dielectric block, wherein each multilayer resonator is in a column shape extending in a first direction into the dielectric block and is formed of multiple metal layers paralleling and overlapping each other in a second direction, and vias extend in the second direction and connecting the metal layers in each multilayer resonator, and a ground electrode connected to the ground terminal of each multilayer resonator.

Abstract: The present invention discloses a dielectric filter with multilayer resonator, including a dielectric block, a plurality of multilayer resonator formed in the dielectric block, wherein each multilayer resonator is in a column shape extending in a first direction into the dielectric block and is formed of multiple metal layers paralleling and overlapping each other in a second direction, and vias extend in the second direction and connecting the metal layers in each multilayer resonator, and a ground electrode connected to the ground terminal of each multilayer resonator.

Abstract: The invention discloses a balance filter formed from a combination of a first circuit and a second circuit, wherein both the first circuit and the second circuit have at least one through-hole via inductor. The balance filter is connected to an IC through a first terminal and a second terminal, wherein a power trace is disposed between the first circuit and the second circuit to deliver the power to the IC.

Abstract: The invention discloses a high-frequency device having a through-hole via inductor in a substrate. The through-hole via inductor has an integral body. The inductance of the through-hole via inductor is greater than that of the horizontal inductor. The through-hole via inductor comprises at least two materials, wherein one of said at least two materials is a conductive material. The present invention also discloses a method for manufacturing the structure of the high-frequency device, wherein the method mainly includes via-drilling and via-filling in the substrate, and lithography process on the substrate.

Abstract: The invention discloses a high-frequency device having a through-hole via inductor in a substrate. The through-hole via inductor has an integral body. The inductance of the through-hole via inductor is greater than that of the horizontal inductor. The through-hole via inductor comprises at least two materials, wherein one of said at least two materials is a conductive material. The present invention also discloses a method for manufacturing the structure of the high-frequency device, wherein the method mainly includes via-drilling and via-filling in the substrate, and lithography process on the substrate.

Abstract: The invention discloses a balance filter formed from a combination of a first circuit and a second circuit, wherein both the first circuit and the second circuit have at least one through-hole via inductor. The balance filter is connected to an IC through a first terminal and a second terminal, wherein a power trace is disposed between the first circuit and the second circuit to deliver the power to the IC.

Abstract: A balun includes a first, second, and third metallic layers, a first dielectric layer disposed between the second and third metallic layers, and a dielectric substrate. The second metallic layer includes a first spiral line having sequentially connected first line segments and a second spiral line having sequentially connected second line segments. A first distance between each two opposite sides of a first region encircled by the innermost first line segments is greater than a second distance between each two adjacent parallel first line segments. A third distance between each two opposite sides of a second region encircled by the innermost second line segments is greater than a fourth distance between each two adjacent parallel second line segments. The third metallic layer includes a third and a fourth spiral lines. The first metallic layer and other elements as a whole are disposed on an opposite surface of the dielectric substrate.

Abstract: A balun includes a first, second, and third metallic layers, a first dielectric layer disposed between the second and third metallic layers, and a dielectric substrate. The second metallic layer includes a first spiral line having sequentially connected first line segments and a second spiral line having sequentially connected second line segments. A first distance between each two opposite sides of a first region encircled by the innermost first line segments is greater than a second distance between each two adjacent parallel first line segments. A third distance between each two opposite sides of a second region encircled by the innermost second line segments is greater than a fourth distance between each two adjacent parallel second line segments. The third metallic layer includes a third and a fourth spiral lines. The first metallic layer and other elements as a whole are disposed on an opposite surface of the dielectric substrate.