Abstract: An apparatus and method for intelligent acceleration of prefetch operations.

Abstract: An apparatus and method for improved snoop handling dynamicity and efficiency. For example, one embodiment of a processor comprises: a plurality of cores; a plurality of caches to store cachelines read from memory by the plurality of cores; cache management circuitry to manage coherency of the cachelines by performing snoops including probes and confirms, the cache management circuitry to: determine a number of outstanding probes and a number of outstanding confirms within a snoop monitoring window; and prioritize confirms over probes or prioritize probes over confirms based, at least in part, on the number of outstanding confirms relative to the number of outstanding probes.

Abstract: An apparatus and method for dynamic prefetching for enhanced workload streaming bandwidth. For example, one example of a method comprises: executing instructions on a first core of a plurality of cores of a processor; initiating, by a last-level cache (LLC) in response to the instructions, a plurality of LLC prefetch operations, each LLC prefetch operation to read a block of cache lines into the LLC; and determining, by mid-level cache (MLC) prefetch circuitry, whether to convert one or more LLC prefetch operations of the plurality of LLC prefetch operations into corresponding MLC prefetch operations based, at least in part, on an LLC hit rate corresponding to the plurality of LLC prefetch operations.

Abstract: Examples described herein relate to a processor that includes a core and a cache, coupled to the core. In some examples, the core is to perform an instruction of a process to specify loads of data from a source to destination regions of caches of a group of target cores. In some examples, the destination regions includes multiple different cache regions and wherein cores of the group of target cores have at least one respective cache.

Abstract: Techniques for loading data with a hint related to data sharing with other cores. For example, one embodiment of an apparatus comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode a single instruction, the single instruction having a first field for an opcode to indicate a load operation to read data from a memory, a second field to indicate a memory address for a location of the data in the memory, and a third field to store a value to indicate whether the data is expected to be shared between the first core and at least a second core of the plurality of cores; execution circuitry to execute the single instruction to read the data from the location in the memory; and cache controller circuitry to store the data in one or more caches in a state selected based on the value.

Abstract: An apparatus and method are described for prefetching data with hints. For example, one embodiment of a processor comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode instructions indicating memory operations including load operations of a first type with shared data hints and load operations of a second type without shared data hints; execution circuitry to execute the instructions to perform the memory operations; data prefetch circuitry to store tracking data in a tracking data structure responsive to the memory operations, a portion of the tracking data associated with the first type of load operations; and the data prefetch circuitry to detect memory access patterns using the tracking data, the data prefetch circuitry to responsively issue one or more prefetch operations using shared data hints based, at least in part, on the portion of the tracking data associated with the first type of load operations.

Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.

Abstract: A processing device implementing silent memory instructions and miss-rate tracking to optimize switching policy on threads is disclosed. A processing device of the disclosure includes a branch prediction unit (BPU) to predict that an instruction of a first thread in a current execution context of the processing device is a delinquent instruction, indicate that the first thread including the delinquent instruction is in a silent execution mode, indicate that the delinquent instruction is to be executed as a silent instruction, switch an execution context of the processing device to a second thread, and when the execution context returns to the first thread, cause the delinquent instruction to be re-executed as a regular instruction.