Patents by Inventor Chen Dan Dong

Chen Dan Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated custom circuit layout enhancement
    Patent number: 10635849
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 28, 2020
    Assignee: Oracle International Corporation
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • AUTOMATED CUSTOM CIRCUIT LAYOUT ENHANCEMENT
    Publication number: 20190272355
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Applicant: Oracle International Corporation
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Automated custom circuit layout enhancement
    Patent number: 10339252
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • AUTOMATED CUSTOM CIRCUIT LAYOUT ENHANCEMENT
    Publication number: 20190065651
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong