Abstract: A metrology system includes a controller communicatively coupled to one or more metrology tools, the controller including one or more processors configured to execute program instructions causing the one or more processors to receive one or more metrology measurements of one or more metrology targets of a metrology sample, a metrology target of the one or more metrology targets including one or more target designs with one or more cells, the one or more target designs being generated on one or more layers of the metrology sample; determine one or more errors based on the one or more metrology measurements; and determine one or more correctables to adjust one or more sources of error corresponding to the one or more errors, the one or more correctables being configured to reduce an amount of noise in the one or more metrology measurements generated by the one or more sources of errors.

Abstract: A metrology system includes a controller communicatively coupled to one or more metrology tools, the controller including one or more processors configured to execute program instructions causing the one or more processors to receive one or more metrology measurements of one or more metrology targets of a metrology sample, a metrology target of the one or more metrology targets including one or more target designs with one or more cells, the one or more target designs being generated on one or more layers of the metrology sample; determine one or more errors based on the one or more metrology measurements; and determine one or more correctables to adjust one or more sources of error corresponding to the one or more errors, the one or more correctables being configured to reduce an amount of noise in the one or more metrology measurements generated by the one or more sources of errors.

Abstract: A device used for semiconductor metrology includes a substrate and a plurality of pieces from one or more semiconductor wafers. Each piece of the plurality of pieces is bonded to the substrate at a respective position on the substrate. Each piece of the plurality of pieces includes a respective instance of a measurement test structure and an alignment mark. Each piece of the plurality of pieces has a known location from the one or more semiconductor wafers.

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.

Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.

Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.