Patents by Inventor Chen-Feng Chang
Chen-Feng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071538Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
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Publication number: 20240074337Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hengyuan Lee, Cheng-Chun Chang, Chen-Feng Hsu, Tung-Ying Lee, Xinyu BAO
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Patent number: 11837299Abstract: An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.Type: GrantFiled: April 8, 2022Date of Patent: December 5, 2023Assignee: Jmem Technology Co., LtdInventor: Chen-Feng Chang
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Publication number: 20220343986Abstract: An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The present invention breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an ith state, and 1 <i <M . The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.Type: ApplicationFiled: April 18, 2022Publication date: October 27, 2022Inventor: Chen-Feng CHANG
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Publication number: 20220328115Abstract: An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.Type: ApplicationFiled: April 8, 2022Publication date: October 13, 2022Inventor: Chen-Feng CHANG
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Patent number: 10032554Abstract: A detachable transformer includes a first bobbin, a primary winding, a second bobbin, a secondary winding and a magnetic core set. The magnetic core set peripherally surrounds the first bobbin and the second bobbin and is inserted into them. A top and a bottom of the first bobbin respectively have a first winding recess and an installation recess. The primary winding is arranged in the first winding recess. A side of the installation recess has a first opening connecting with an external space. A top of the second bobbin has a second winding recess. The secondary winding is arranged in the second winding recess. The second bobbin is arranged in the installation recess through the first opening, whereby the first bobbin and the second bobbin form a detachable connection.Type: GrantFiled: August 11, 2016Date of Patent: July 24, 2018Assignee: MEAN WELL (GUANGZHOU) ELECTRONICS CO., LTD.Inventors: Yu-Hsiang Lee, Chen-Feng Chang
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Publication number: 20180047501Abstract: A detachable transformer includes a first bobbin, a primary winding, a second bobbin, a secondary winding and a magnetic core set. The magnetic core set peripherally surrounds the first bobbin and the second bobbin and is inserted into them. A top and a bottom of the first bobbin respectively have a first winding recess and an installation recess. The primary winding is arranged in the first winding recess. A side of the installation recess has a first opening connecting with an external space. A top of the second bobbin has a second winding recess. The secondary winding is arranged in the second winding recess. The second bobbin is arranged in the installation recess through the first opening, whereby the first bobbin and the second bobbin form a detachable connection.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Inventors: Yu-Hsiang LEE, Chen-Feng CHANG
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Patent number: 8875083Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.Type: GrantFiled: October 3, 2013Date of Patent: October 28, 2014Assignee: Synopsys, Inc.Inventors: Chen-Feng Chang, Chin-Fang Shen, Hsien-Shih Chiu, I-Jye Lin, Tien-Chang Hsu, Yao-Wen Chang, Chun-Wei Lin, Po-Wei Lee
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Publication number: 20140033156Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.Type: ApplicationFiled: October 3, 2013Publication date: January 30, 2014Applicant: SYNOPSYS, INC.Inventors: Chen-Feng Chang, Chin-Fang Shen, Hsien-Shih Chiu, I-Jye Lin, Tien-Chang Hsu, Yao-Wen Chang, Chun-Wei Lin, Po-Wei Lee
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Patent number: 8578317Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.Type: GrantFiled: October 27, 2010Date of Patent: November 5, 2013Assignee: Synopsys, Inc.Inventors: Chen-Feng Chang, Chin-Fang Shen, Hsien-Shih Chiu, I-Jye Lin, Tien-Chang Hsu, Yao-Wen Chang, Chun-Wei Lin, Po-Wei Lee
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Publication number: 20120216167Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.Type: ApplicationFiled: October 27, 2010Publication date: August 23, 2012Applicant: SYNOPSYS, INC.Inventors: Chen-Feng Chang, Chin-Fang Shen, Hsien-Shih Chiu, I-Jye Lin, Tien-Chang Hsu, Yao-Wen Chang, Chun-Wei Lin, Po-Wei Lee