Abstract: A pixel array substrate includes a substrate, a first patterned conductive layer, a pixel electrode layer, a semiconductor pattern layer, a first dielectric layer, a second patterned conductive layer, a second dielectric layer, and a common electrode layer. The first patterned conductive layer includes first and second scan lines, first and second gates, and first and second connection electrodes. The pixel electrode layer includes first and second pixel electrodes. The semiconductor pattern layer includes first and second patterns. The second patterned conductive layer includes first and second data lines, first and second sources, first and second drains, and a touch wire. The common electrode layer includes a common electrode and first and second transferring electrodes. The first transferring electrode is electrically connected to the first connection electrode and the first drain. The second transferring electrode is electrically connected to the second connection electrode and the second drain.

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor.

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: A pixel array substrate includes a substrate, a first patterned conductive layer, a pixel electrode layer, a semiconductor pattern layer, a first dielectric layer, a second patterned conductive layer, a second dielectric layer, and a common electrode layer. The first patterned conductive layer includes first and second scan lines, first and second gates, and first and second connection electrodes. The pixel electrode layer includes first and second pixel electrodes. The semiconductor pattern layer includes first and second patterns. The second patterned conductive layer includes first and second data lines, first and second sources, first and second drains, and a touch wire. The common electrode layer includes a common electrode and first and second transferring electrodes. The first transferring electrode is electrically connected to the first connection electrode and the first drain. The second transferring electrode is electrically connected to the second connection electrode and the second drain.

Abstract: A pixel circuit includes a first switch, a storage circuit, a second switch, and a liquid crystal capacitor. The first node of the first switch is configured to receive a data signal, and the second node of the first switch is coupled with a first node point. The storage circuit is coupled with the first node point, and configured to receive a common voltage. The first node of the second switch is coupled with the storage circuit, and the second node of the second switch is configured to receive a boost signal. The liquid crystal capacitor is coupled between the first node point and the storage circuit. In response to the first switch is conducted, the second switch is conducted, or in response to the second switch is conducted, the first switch is conducted.

Abstract: A control circuit includes a switching circuit and a select circuit. The switching circuit is configured to receive a scan signal, a first switching signal, and a second switching signal, and output the first switching signal and the second switching signal according to the scan signal. The select circuit is configured to receive a first supply voltage, a second supply voltage, the first switching signal, and the second switching signal, and selectively output the first supply voltage or the second supply voltage to a target electrode according to the first switching signal and the second switching signal.

Abstract: A pixel circuit includes a first switch, a storage circuit, a second switch, and a liquid crystal capacitor. The first node of the first switch is configured to receive a data signal, and the second node of the first switch is coupled with a first node point. The storage circuit is coupled with the first node point, and configured to receive a common voltage. The first node of the second switch is coupled with the storage circuit, and the second node of the second switch is configured to receive a boost signal. The liquid crystal capacitor is coupled between the first node point and the storage circuit. In response to the first switch is conducted, the second switch is conducted, or in response to the second switch is conducted, the first switch is conducted.

Abstract: A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor.

Abstract: A pixel structure includes first and second gate lines, at least one data line, and a pixel unit. The pixel unit has first and second display areas and includes first and second active devices, a first pixel electrode layer, a common electrode layer, and a second pixel electrode layer. The first and second active devices are electrically connected to the first and second gate lines, respectively. The first pixel electrode layer is electrically connected to the first active device. The common electrode layer is disposed above the first pixel electrode layer and includes first and second portions which are located at the first and second display areas, respectively. The second pixel electrode layer is electrically connected to the second active device, and is located above the first portion of the common electrode layer but not above the second portion, where the second pixel electrode layer has a first slit pattern and the second portion of the common electrode layer has a second slit pattern.

Abstract: A liquid crystal display panel includes first and second substrates, first pixel electrodes, second pixel electrodes, common electrodes, first auxiliary electrodes, and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first and the second substrates. The first pixel electrodes, the second pixel electrodes, and the common electrodes are disposed on the first substrate. The first auxiliary electrodes are disposed on the second substrate. One of the first pixel electrodes is not overlapping one of the first auxiliary electrodes in a vertical projection direction and overlapping one of the common electrodes in the vertical projection direction. A driving method of the liquid crystal display panel includes setting a first voltage difference in a wide viewing mode and a second voltage difference in a narrow viewing mode between the first auxiliary electrodes and the common electrodes.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.

Abstract: A pixel structure includes first and second gate lines, at least one data line, and a pixel unit. The pixel unit has first and second display areas and includes first and second active devices, a first pixel electrode layer, a common electrode layer, and a second pixel electrode layer. The first and second active devices are electrically connected to the first and second gate lines, respectively. The first pixel electrode layer is electrically connected to the first active device. The common electrode layer is disposed above the first pixel electrode layer and includes first and second portions which are located at the first and second display areas, respectively. The second pixel electrode layer is electrically connected to the second active device, and is located above the first portion of the common electrode layer but not above the second portion, where the second pixel electrode layer has a first slit pattern and the second portion of the common electrode layer has a second slit pattern.

Abstract: A liquid crystal display panel includes first and second substrates, first pixel electrodes, second pixel electrodes, common electrodes, first auxiliary electrodes, and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first and the second substrates. The first pixel electrodes, the second pixel electrodes, and the common electrodes are disposed on the first substrate. The first auxiliary electrodes are disposed on the second substrate. One of the first pixel electrodes is not overlapping one of the first auxiliary electrodes in a vertical projection direction and overlapping one of the common electrodes in the vertical projection direction. A driving method of the liquid crystal display panel includes setting a first voltage difference in a wide viewing mode and a second voltage difference in a narrow viewing mode between the first auxiliary electrodes and the common electrodes.

Abstract: A control circuit includes a switching circuit and a select circuit. The switching circuit is configured to receive a scan signal, a first switching signal, and a second switching signal, and output the first switching signal and the second switching signal according to the scan signal. The select circuit is configured to receive a first supply voltage, a second supply voltage, the first switching signal, and the second switching signal, and selectively output the first supply voltage or the second supply voltage to a target electrode according to the first switching signal and the second switching signal.

Abstract: A liquid crystal display panel includes first and second substrates, first pixel electrodes, second pixel electrodes, common electrodes, first auxiliary electrodes, and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first and the second substrates. The first pixel electrodes, the second pixel electrodes, and the common electrodes are disposed on the first substrate. The first auxiliary electrodes are disposed on the second substrate. One of the first pixel electrodes is not overlapping one of the first auxiliary electrodes in a vertical projection direction. A driving method of the liquid crystal display panel includes setting a first voltage difference in a wide viewing mode and a second voltage difference in a narrow viewing mode between the first auxiliary electrodes and the common electrodes and, respectively. The first voltage difference is less than the second voltage difference.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.

Abstract: A liquid crystal display panel includes first and second substrates, first pixel electrodes, second pixel electrodes, common electrodes, first auxiliary electrodes, and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first and the second substrates. The first pixel electrodes, the second pixel electrodes, and the common electrodes are disposed on the first substrate. The first auxiliary electrodes are disposed on the second substrate. One of the first pixel electrodes is not overlapping one of the first auxiliary electrodes in a vertical projection direction. A driving method of the liquid crystal display panel includes setting a first voltage difference in a wide viewing mode and a second voltage difference in a narrow viewing mode between the first auxiliary electrodes and the common electrodes and, respectively. The first voltage difference is less than the second voltage difference.

Abstract: Disclosed herein is a display device with an adjustable viewing angle. The display device at least includes a first sub-pixel and a second sub-pixel adjacent to the first sub-pixel. When the display device is operated in a wide viewing angle mode, the first and second sub-pixels each have an on-axis brightness at a predetermined gray level. When the display device is operated in a narrow viewing angle mode, the first and second sub-pixels respectively have a on-axis brightness at a first gray level and a second on-axis brightness at a second gray level. The on-axis brightness at the first gray level is substantially less than the on-axis brightness at the predetermined gray level of the first sub-pixel.

Abstract: A peep-proof display apparatus includes a plurality of sub-pixels disposed between a first substrate and a second substrate. Each sub-pixel includes a first conductive layer, a color filter layer, an isolation film, a light modulator layer, a second conductive layer, an insulation film and a third conductive layer. The color filter layer is disposed between the first conductive layer and the isolation film. The light modulator layer is disposed between the isolation film and the second conductive layer. The insulation film is disposed between the second and third conductive layers. In a first display mode, the light modulator layer is applied with an electric field parallel thereto. In a second display mode, the light modulator layer is applied with an electric field parallel thereto and an electric field perpendicular thereto.