Patents by Inventor Chen-Fu Hsu
Chen-Fu Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11916060Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.Type: GrantFiled: June 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
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Patent number: 8669150Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: GrantFiled: December 21, 2012Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Patent number: 8338243Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: GrantFiled: May 9, 2011Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Publication number: 20110212585Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: ApplicationFiled: May 9, 2011Publication date: September 1, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Patent number: 7960810Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: GrantFiled: September 5, 2006Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Patent number: 7553733Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.Type: GrantFiled: April 4, 2007Date of Patent: June 30, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Ren Tsai, Chen-Fu Hsu
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Publication number: 20080054399Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: ApplicationFiled: September 5, 2006Publication date: March 6, 2008Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Publication number: 20070181919Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.Type: ApplicationFiled: April 4, 2007Publication date: August 9, 2007Inventors: Ming-Ren Tsai, Chen-Fu Hsu
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Patent number: 7224025Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.Type: GrantFiled: August 3, 2004Date of Patent: May 29, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Ren Tsai, Chen-Fu Hsu
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Publication number: 20060049452Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes forming a plurality of wells on a semiconductor substrate. The plurality of wells include a first well of a first type, a second well of a second type opposite to the first type, and a third well of the first type. The device includes a gate to control flow from current from a source to a drain. Highly doped regions of the first type provide contacts for the source and the drain. The third well, which is disposed in between the second well, is formed directly below the highly doped region. The third well causes an energy barrier at the source to decrease, thereby resulting in lowering a threshold voltage of the LDMOS device compared to the LDMOS device without the third well.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Inventors: Ming-Ren Tsai, Chen-Fu Hsu
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Publication number: 20060027874Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between the gate and the drain. The gate is formed over a first portion of the well of the first type and a channel portion of the well of the second type. The LDMOS also includes a second field oxide region, which is disposed between the edges of the drain and the well of the second type. A dummy polysilicon layer, which is formed to cover approximately one half of the second field oxide with a remaining portion of the dummy polysilicon layer covering a second portion of the well of the second type, reduces the electric field in the drift region.Type: ApplicationFiled: August 3, 2004Publication date: February 9, 2006Inventors: Ming-Ren Tsai, Chen-Fu Hsu
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Publication number: 20050242444Abstract: Provided is an integrated circuit (IC) having a strengthened passivation layer. In one example, the IC comprises a semiconductor substrate, a multilevel interconnect structure formed on the semiconductor substrate, and a multilayer passivation structure overlying the multilevel interconnect structure. At least one metal line of the multilevel interconnect structure forms a taper profile.Type: ApplicationFiled: October 14, 2004Publication date: November 3, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kun-Ming Huang, Chen-Fu Hsu