Patents by Inventor Chen Han

Chen Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240241098
    Abstract: A wall mountable sensor module includes a housing defining an internal space that is segmented into a first internal space and a second internal space. The first internal space defines an air channel that extends from an air inlet to an air outlet. Two or more sensors are configured to be exposed to the air flow channel. A first sensor is configured to detect a first air parameter and a second sensor is configured to detect a second different air parameter, wherein the second sensor is situated downstream of the first sensor in the air flow channel. The sensor module includes a fan housed by the housing, the fan configured to cause an airflow to flow in through the air inlet, through the air flow channel thereby exposing each of the sensors to the airflow, and out through the air outlet.
    Type: Application
    Filed: October 11, 2022
    Publication date: July 18, 2024
    Inventors: Chao Chen, Yu Zhi Yan, Hua Tang, Kaixuan Qin, Zhi Yi Sun, Jian Wang, Ke Wei Han, Qixiang Hu
  • Publication number: 20240241771
    Abstract: The specification provides a method includes: updating a depth value of a target node or a depth value of a downstream node of the target node; receiving a depth value sent by an upstream node of the target node, and comparing the depth value of the target node with the depth value sent by the upstream node of the target node; in response to that the depth value of the target node is less than the depth value sent by the upstream node of the target node, updating the depth value of the target node to the depth value sent by the upstream node of the target node; and in response to that the depth value of the target node is equal to the depth value sent by the upstream node of the target node, determining that a loop exists in a data dependency path including the target node.
    Type: Application
    Filed: May 7, 2022
    Publication date: July 18, 2024
    Inventors: Zhenkun YANG, Chen QIAN, Xuwang TENG, Fanyu KONG, Fusheng HAN
  • Publication number: 20240243011
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Application
    Filed: February 26, 2024
    Publication date: July 18, 2024
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20240243466
    Abstract: A wireless briefing device includes a first antenna, a second antenna, and a ground plane. Each of the first antenna and the second antenna couples out a frequency band. A distance between the first antenna and the ground plane is between 0.2 and 0.3 times of a wavelength of the frequency band, and a distance between the second antenna and the ground plane is between 0.2 and 0.3 times of the wavelength of the frequency band.
    Type: Application
    Filed: June 19, 2023
    Publication date: July 18, 2024
    Applicant: BENQ CORPORATION
    Inventors: Yu-Ping Huang, Chun-Han Lin, Chen-Chi Wu, Chia-Nan Shih, Cheng-Pu Lin
  • Patent number: 12038687
    Abstract: A method for building an etching-free hybrid nonlinear waveguide composed of a polymer and an ion-implanted nonlinear crystal is provided. A nonlinear crystal is pretreated, and subjected to ion implantation to obtain an ion-implanted nonlinear crystal. The ion-implanted nonlinear crystal is spin-coated with a photoresist, and subjected to electron beam exposure, heating, and developing, so as to obtain a hybrid optical waveguide composed of a polymer and a nonlinear crystal.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: July 16, 2024
    Assignee: SHANDONG NORMAL UNIVERSITY
    Inventors: Chen Chen, Zhanghua Han, Shengkun Yao, Feng Chen
  • Publication number: 20240227338
    Abstract: A fully-automatic production line and an automatic production method for rubber sealing rings. The fully-automatic production line includes a ring forming area, a molded vulcanization area, a flash removal area, a two-stage vulcanization area, an online detection area, a packaging and labeling area, and a control room. An automatic production line for rubber sealing rings involves the steps of loading and transferring, molded vulcanization, flash removal, second-stage vulcanization, packaging and labeling, and the like. The fully-automatic production line solves the technical problems in the prior art that the production of rubber sealing rings fails to adopt the molded vulcanization process, and meanwhile the specifications of the produced rubber sealing rings are single.
    Type: Application
    Filed: November 7, 2023
    Publication date: July 11, 2024
    Inventors: Xiaofeng ZHANG, Jie ZHONG, Chen HAN, Bing LI, Liang WANG, Jiangxiong LUO, Chun XU, Yong HUANG, Xi LING, Zhe CHEN, Qianqian XU, Qingbo ZHENG, Siyu LIN, Qin CHEN, Xing LIU
  • Publication number: 20240226679
    Abstract: A paddle racket is provided, including: a frame body, including a frame wall and a handle connected to the frame wall, the frame wall having an inner circumferential surface and defining a receiving space; a three-dimensional web core, disposed in the receiving space and including an outer circumferential surface facing the inner circumferential surface, including channels disposed through the three-dimensional web core in a thickness direction of the three-dimensional web core; two striking surface portions, disposed on two opposing sides of the three-dimensional web core, each striking surface portions including through holes, the through holes corresponding to and being in communication with parts of the channels; and double-sided adhesive layers, connecting the outer circumferential surface of the three-dimensional web core to the inner circumferential surface of the frame wall and connecting the two striking surface portions to the two opposing sides of the three-dimensional web core.
    Type: Application
    Filed: February 6, 2023
    Publication date: July 11, 2024
    Inventor: Chen-Han LIN
  • Publication number: 20240170323
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal Abhijith KHADERBAD, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240160660
    Abstract: A data classification method, for classifying unlabeled images into an inlier data set or an outlier data set, include following steps. The unlabeled images are obtained. An assigned inlier image is selected among the unlabeled images. A similarity matrix is computed and the similarity matrix includes first similarity scores of the unlabeled images relative to the assigned inlier image. Each of the unlabeled images is classified into an inlier data set or an outlier data set according to the similarity matrix, so as to generate inlier-outlier predictions of the unlabeled images.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Chen-Han TSAI, Yu-Shao PENG
  • Publication number: 20240162083
    Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chen-Han WANG, Keng-Chu LIN, Tetsuji UENO, Ting-Ting CHEN
  • Publication number: 20240119267
    Abstract: Apparatuses, systems, and techniques to selectively use one or more neural network layers. In at least one embodiment, one or more neural network layers are selectively used based on, for example, one or more iteratively increasing neural network performance metrics.
    Type: Application
    Filed: September 21, 2022
    Publication date: April 11, 2024
    Inventors: Slawomir Kierat, Piotr Karpinski, Mateusz Sieniawski, Pawel Morkisz, Szymon Migacz, Linnan Wang, Chen-Han Yu, Satish Salian, Ashwath Aithal, Alexandru Fit-Florea
  • Patent number: 11946246
    Abstract: The present invention provides an energy-storing temperature control material, and belongs to the technical field of temperature control materials. In the energy-storing temperature control material provided in the present invention, the organic synthetic fiber based phase-change material has a three-dimensional dispersion effect, and can form a network constraint for remaining phase-change materials to reinforce mechanical properties of the materials, thereby fixing shapes of the materials and avoiding a liquid-crystal phase separation phenomenon in the phase-change process. The phase-change energy storage agent can absorb and release the heat by means of solid-liquid phase conversion of the material, to achieve the temperature control effect; and the phase-change temperature regulator can regulate a phase-change temperature range of the phase-change material, to make the energy-storing temperature control material suitable for climatic features of northern China.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Qilu University of Technology
    Inventors: Letian Qi, Shoujuan Wang, Xia Meng, Fangong Kong, Ruhe Zhao, Chen Han, Debao Li
  • Patent number: 11942358
    Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Ko-Feng Chen, Zheng-Yong Liang, Chen-Han Wang, De-Yang Chiou, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20240087955
    Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Yi XU, Xianyuan ZHAO, Zhimin QI, Aixi ZHANG, Geraldine VASQUEZ, Dien-Yeh WU, Wei LEI, Xingyao GAO, Shirish PETHE, Wenting HOU, Chao DU, Tsung-Han YANG, Kyoung-Ho BU, Chen-Han LIN, Jallepally RAVI, Yu LEI, Rongjun WANG, Xianmin TANG
  • Publication number: 20240049664
    Abstract: The Intelligent Aeroponic Microgravity & Earth Nutrient Delivery (I-AMEND) System is configured to enable the productive growth of crops on the Moon, Mars, and beyond as well as in space stations in low-Earth orbit, such as the International Space Station (ISS), and also on Earth. Principal components of the I-AMEND system may include an aeroponic chamber, a liquid nutrient emitter for emission of a liquid into the aeroponic chamber, and an air emitter for emission of a gust of air into the aeroponic system. The emitters may be positioned upstream or downstream of a plant port of the aeroponic chamber so as to direct the liquid onto or off of a surface of the plant root.
    Type: Application
    Filed: February 23, 2022
    Publication date: February 15, 2024
    Inventors: Joel L. Cuello, Yaser Mehdipour, Chen-Han Shih, Jack Welchert, Kate Stalkfleet, Sean Gellenbeck, Torin Hodge
  • Patent number: 11901220
    Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chen-Han Wang, Keng-Chu Lin, Tetsuji Ueno, Ting-Ting Chen
  • Publication number: 20240009906
    Abstract: The present invention relates to the field of forming technologies for rubber sealing ring blanks, and more particularly to an automatic forming method and device for a rubber sealing ring blank. A cutting blade is fixedly connected to the surface of a blank forming assembly; an equipment body II is fixedly connected to a sliding table die set; a supporting rod II is fixedly connected to the surface of the equipment body II; a blank box is fixedly connected to the inner side surface of the supporting rod II; and a blank spool is fixedly connected to the tail end of a long blank strip. The method and device disclosed by the present invention have the advantages that the automation degree is high, and the long blank strip conveyed from the blank spool passes through guide wheels and a guide groove and is automatically pressed into a ring through the combined action of the blank forming assembly and the cutting blade.
    Type: Application
    Filed: March 20, 2023
    Publication date: January 11, 2024
    Inventors: Liang WANG, Hongzhong TU, Jie ZHONG, Chen HAN, Junjie LI, Xiaofeng ZHANG, Zhulin XU, Wenfeng WU, Yanhui CHEN, Xuanmin HUANG, Xi LING, Shixiang GAN, Donghui LI, Jiajun XIE, Qingbo ZHENG, Dongliang DING, Shipu GUO
  • Patent number: 11848238
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Han Wang, Keng-Chu Lin, Shuen-Shin Liang, Tetsuji Ueno, Ting-Ting Chen
  • Publication number: 20230396250
    Abstract: The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 7, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chen-Han Tsai, Chia-Hao Hsu, Zhi-Gang Zeng, Cheng-Tang Chen
  • Publication number: 20230378056
    Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN