Patents by Inventor Chen Han

Chen Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974329
    Abstract: Disclosed is a network access method, including that a station receives a first radio frame from a first access point, where the first radio frame indicates a resource unit for a random-access operation; and when the sending address of the first radio frame is a public identity or a private identity, the station performs the random-access operation. Also disclosed are a network access apparatus and a storage medium.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: April 30, 2024
    Assignee: ZTE Corporation
    Inventors: Zhiqiang Han, Kaiying Lv, Bo Sun, Chen Lu
  • Publication number: 20240137592
    Abstract: An information processing method of the present disclosure includes: via one or more computer processors, receiving data relating to live sales performed by a livestreamer via live video streaming; inputting the data into a machine learning model; and based on a result generated by the machine learning model, obtaining promotional information that is useful for the livestreamer to perform the live sales.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 25, 2024
    Inventors: Yung-Chi HSU, Chia-Han CHANG, Chen-Hai TENG
  • Patent number: 11967613
    Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: April 23, 2024
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Ju-Hsien Lin, Jung-Tao Chung, Shu-Hsiao Tsai, Hsi-Tsung Lin, Chen-An Hsieh, Yi-Han Chen, Yao-Ting Shao
  • Patent number: 11967599
    Abstract: An array substrate and a display panel. The array substrate provided in the embodiments of the present application includes: a base including a flat portion and a recess portion so that the base includes a concave hole corresponding to the bending area; a semiconductor component layer provided on the base and including a plurality of interlayer insulation layers and a plurality of metal layers, the interlayer insulation layers being not aligned horizontally in the peripheral area and the wire switching area to form a stepped hole including a first hole and a second hole, wherein a third metal layer of the metal layers extends along a sidewall and a bottom of the stepped hole and is electrically connected to a first metal layer of the metal layers.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: April 23, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Jinfang Zhang, Chen Zhang, Zhiwei Chen, Lu Zhang, Siming Hu, Zhenzhen Han
  • Patent number: 11966340
    Abstract: To automate time series forecasting machine learning pipeline generation, a data allocation size of time series data may be determined based on one or more characteristics of a time series data set. The time series data may be allocated for use by candidate machine learning pipelines based on the data allocation size. Features for the time series data may be determined and cached by the candidate machine learning pipelines. Predictions of each of the candidate machine learning pipelines using at least the one or more features may be evaluated. A ranked list of machine learning pipelines may be automatically generated from the candidate machine learning pipelines for time series forecasting based upon evaluating predictions of each of the one or more candidate machine learning pipelines.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Long Vu, Bei Chen, Xuan-Hong Dang, Peter Daniel Kirchner, Syed Yousaf Shah, Dhavalkumar C. Patel, Si Er Han, Ji Hui Yang, Jun Wang, Jing James Xu, Dakuo Wang, Gregory Bramble, Horst Cornelius Samulowitz, Saket K. Sathe, Wesley M. Gifford, Petros Zerfos
  • Publication number: 20240125916
    Abstract: An indoor positioning method includes scanning for registered Wi-Fi nodes with known coordinates to generate a list of the registered Wi-Fi nodes. The method also includes performing a ranging operation by (i) selecting nodes to range with from the list of the registered Wi-Fi nodes, and (ii) processing ranging responses from the selected nodes to generate a series of distance measurements. The method further includes obtaining a series of sensor readings generated by one or more inertial measurement units (IMUs) of a device. The method also includes estimating a position of the device based on the series of distance measurements and the series of sensor readings using first and second filtering operations that are performed in parallel.
    Type: Application
    Filed: June 27, 2023
    Publication date: April 18, 2024
    Inventors: Rebal Al Jurdi, Hao Chen, Jianyuan Yu, Boon Loong Ng, Kyu-Hui Han, Jianzhong Zhang
  • Publication number: 20240119267
    Abstract: Apparatuses, systems, and techniques to selectively use one or more neural network layers. In at least one embodiment, one or more neural network layers are selectively used based on, for example, one or more iteratively increasing neural network performance metrics.
    Type: Application
    Filed: September 21, 2022
    Publication date: April 11, 2024
    Inventors: Slawomir Kierat, Piotr Karpinski, Mateusz Sieniawski, Pawel Morkisz, Szymon Migacz, Linnan Wang, Chen-Han Yu, Satish Salian, Ashwath Aithal, Alexandru Fit-Florea
  • Patent number: 11955385
    Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
  • Patent number: 11956972
    Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Ching-Hua Hsu, Chen-Yi Weng, Po-Kai Hsu
  • Publication number: 20240112330
    Abstract: The present invention relates to a method for screening mobile terminal visual attention abnormalities in children based on multimodal data learning. A calibration video and a testing video are set up, and a head-face video of children while watching the calibration video and the testing video on smartphones is recorded, respectively. An eye-tracking estimation model is constructed to predict the fixation point location from the head-face video corresponding to the testing video frame by frame and to extract the eye-tracking features. Facial expression features and head posture features are extracted. A Long Short-Term Memory (LSTM) network is used to fuse different modal features and realize the mapping from multimodal features to category labels. In the testing stage, the head-face video of children to be classified while watching the videos on smartphones is recorded, and the features are extracted and input into the post-training model to determine whether they are abnormal.
    Type: Application
    Filed: July 11, 2023
    Publication date: April 4, 2024
    Inventors: CHEN XIA, HEXU CHEN, JUNWEI HAN, LEI GUO, KUAN LI, CHI ZHANG, ZHIHONG XU
  • Publication number: 20240114622
    Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Cary Kuliasha, Siddharth K. Alur, Jung Kyu Han, Beomseok Choi, Russell K. Mortensen, Andrew Collins, Haobo Chen, Brandon C. Marin
  • Patent number: 11946246
    Abstract: The present invention provides an energy-storing temperature control material, and belongs to the technical field of temperature control materials. In the energy-storing temperature control material provided in the present invention, the organic synthetic fiber based phase-change material has a three-dimensional dispersion effect, and can form a network constraint for remaining phase-change materials to reinforce mechanical properties of the materials, thereby fixing shapes of the materials and avoiding a liquid-crystal phase separation phenomenon in the phase-change process. The phase-change energy storage agent can absorb and release the heat by means of solid-liquid phase conversion of the material, to achieve the temperature control effect; and the phase-change temperature regulator can regulate a phase-change temperature range of the phase-change material, to make the energy-storing temperature control material suitable for climatic features of northern China.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Qilu University of Technology
    Inventors: Letian Qi, Shoujuan Wang, Xia Meng, Fangong Kong, Ruhe Zhao, Chen Han, Debao Li
  • Publication number: 20240105901
    Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Chen-Hua Yu, Keng-Han Lin, Hung-Jui Kuo, Hui-Jung Tsai
  • Patent number: 11941880
    Abstract: A system and a method for image-based crop identification are disclosed. The image-based crop identification system includes a database, a communication module and a model library. The database stores sample aerial data and annotated aerial data. The communication module is coupled to the database, and is configured to provide the sample aerial data to a user and receive the annotated aerial data from the user. The model library is coupled to the database, and is configured to obtain the annotated aerial data, train a crop classification model based on the annotated aerial data, and provide the trained crop classification model for subsequent crop identification. The annotated aerial data include determination of the type of the crop appearing in the sample aerial data.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 26, 2024
    Assignee: PING AN TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventors: Chen Du, Jui-Hsin Lai, Mei Han
  • Patent number: 11942363
    Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
  • Publication number: 20240099154
    Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240084072
    Abstract: A compound of formula (I), wherein R1R2R3 are defined in the disclosure. The compound of formula (I) is used as a catalyst for lactide polymerization to reduce the temperature and the time of the polymerization reaction, thereby producing polylactic acid (PLA) having high molecular weight. The present invention also provides a method of preparing the compound of formula (1) and a method of synthesizing polylactic acid that is catalyzed by the compound of formula (1).
    Type: Application
    Filed: October 31, 2022
    Publication date: March 14, 2024
    Applicant: Plastics Industry Development Center
    Inventors: CHEN-YU LI, PO-HAN LI, YU-LI LEE
  • Publication number: 20240087955
    Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Yi XU, Xianyuan ZHAO, Zhimin QI, Aixi ZHANG, Geraldine VASQUEZ, Dien-Yeh WU, Wei LEI, Xingyao GAO, Shirish PETHE, Wenting HOU, Chao DU, Tsung-Han YANG, Kyoung-Ho BU, Chen-Han LIN, Jallepally RAVI, Yu LEI, Rongjun WANG, Xianmin TANG
  • Publication number: 20240088052
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN