Patents by Inventor CHEN HAN CHOU
CHEN HAN CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12211789Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.Type: GrantFiled: July 31, 2023Date of Patent: January 28, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
-
Publication number: 20240395698Abstract: A method includes following steps. A dielectric layer is formed over a substrate. A transition metal-containing layer is deposited on the dielectric layer. The transition metal-containing layer is patterned into a plurality of transition metal-containing pieces. The transition metal-containing pieces are sulfurized or selenized to form a plurality of semiconductor seeds. Semiconductor films are grown from semiconductor seeds. Transistors are formed on the semiconductor films.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
-
Patent number: 12154828Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.Type: GrantFiled: January 13, 2022Date of Patent: November 26, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chiung-Yuan Lin, Tsung-Fu Yang, Weicheng Chu, Ching Liang Chang, Chen Han Chou, Chia-Ho Yang, Tsung-Kai Lin, Tsung-Han Lin, Chih-Hung Chung, Chenming Hu
-
Publication number: 20230378056Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
-
Patent number: 11784119Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.Type: GrantFiled: August 23, 2021Date of Patent: October 10, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming Hu, Shu-Jui Chang, Chen-Han Chou, Yen-Teng Ho, Chia-Hsing Wu, Kai-Yu Peng, Cheng-Hung Shen
-
Publication number: 20230023186Abstract: A semiconductor device includes a substrate, a 2-D material layer, source/drain contacts, and a gate electrode. The 2-D material layer is over the substrate, the 2-D material layer includes source/drain regions and a channel region between the source/drain regions, in which the 2-D material layer is made of a transition metal dichalcogenide (TMD). The source/drain contacts are in contact with source/drain regions of the 2-D material layer, in which a binding energy of transition metal atoms at the channel region of the 2-D material layer is different from a binding energy of the transition metal atoms at the source/drain regions of the 2-D material layer. The gate electrode is over the substrate.Type: ApplicationFiled: January 13, 2022Publication date: January 26, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., National Yang Ming Chiao Tung UniversityInventors: Chiung-Yuan LIN, Tsung-Fu YANG, Weicheng CHU, Ching Liang CHANG, Chen Han CHOU, Chia-Ho YANG, Tsung-Kai LIN, Tsung-Han LIN, Chih-Hung CHUNG, Chenming HU
-
Publication number: 20230008409Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.Type: ApplicationFiled: March 23, 2022Publication date: January 12, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chen Han CHOU, Shu-Jui CHANG, Yen-Teng HO, Chia Hsing WU, Kai-Yu PENG, Cheng Hung SHEN, Chenming HU
-
Publication number: 20220319982Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.Type: ApplicationFiled: August 23, 2021Publication date: October 6, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Chenming HU, Shu-Jui CHANG, Chen-Han CHOU, Yen-Teng HO, Chia-Hsing WU, Kai-Yu PENG, Cheng-Hung SHEN
-
Patent number: 10269966Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: GrantFiled: November 8, 2017Date of Patent: April 23, 2019Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
-
Publication number: 20180069114Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
-
Patent number: 9859276Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: GrantFiled: October 13, 2016Date of Patent: January 2, 2018Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Chiao-Tung UniversityInventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
-
Patent number: 9837538Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: GrantFiled: July 20, 2016Date of Patent: December 5, 2017Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
-
Publication number: 20170278962Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.Type: ApplicationFiled: July 20, 2016Publication date: September 28, 2017Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
-
Publication number: 20170125415Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: ApplicationFiled: October 13, 2016Publication date: May 4, 2017Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN
-
Patent number: 9502502Abstract: Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate.Type: GrantFiled: March 16, 2015Date of Patent: November 22, 2016Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung UniversityInventors: Samuel C. Pan, Chao-Hsin Chien, Chen-Han Chou
-
Patent number: 9496259Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: GrantFiled: April 14, 2015Date of Patent: November 15, 2016Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO-TUNG UNIVERSITYInventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
-
Publication number: 20160307894Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.Type: ApplicationFiled: April 14, 2015Publication date: October 20, 2016Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN
-
Patent number: 9460928Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.Type: GrantFiled: February 3, 2015Date of Patent: October 4, 2016Assignee: Macronix International Co., Ltd.Inventors: Chen-Han Chou, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
-
Publication number: 20160276436Abstract: Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Samuel C. Pan, Chao-Hsin Chien, Chen-Han Chou
-
Publication number: 20160225627Abstract: A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface of the substrate and have a height measured from the surface of the substrate. The method further includes determining an interval distribution representing a distribution of intervals between neighboring projections and calculating an implantation angle based on the height and the interval distribution. The implantation angle is an angle between a normal direction of the substrate and an implantation direction. The method also includes implanting ions at the calculated implantation angle.Type: ApplicationFiled: February 3, 2015Publication date: August 4, 2016Inventors: Chen-Han CHOU, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu