Abstract: A semiconductor structure includes a substrate, and an active device and a passive device over the substrate. The active device is disposed in a first region of the substrate, and the passive device is disposed in a second region of the substrate. The semiconductor structure further includes a shielding structure and a passivation layer. The shielding structure includes a barrier layer and a ceiling layer. The barrier layer is on the passive device and the active device, and the ceiling layer is on the barrier layer. The passivation layer is under the barrier layer and covers a top surface of the passive device. An air cavity is defined by sidewalls of the barrier layer, a bottom surface of the ceiling layer, and the substrate.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: The present invention provides a clock buffer, wherein the clock buffer receives an input signal at a first node and generate an output signal at a second node. The clock buffer includes a P-type transistor, a first N-type transistor, a resistor, a transistor and a switch. A source electrode, a gate electrode and a drain electrode of the P-type transistor are coupled to a supply voltage, the first node, and the second node, respectively. A gate electrode, a drain electrode and a source electrode of the first N-type transistor are coupled to the first node, the second node and a third node, respectively. The resistor is coupled between the first node and the second node. The transistor is coupled between the first N-type transistor and a ground voltage. The switch is configured to selectively connect the third node to the ground voltage.

Abstract: A medical image detection system includes a memory and a processor. The processor is configured to execute the neural network model stored in the memory. The neural network model includes a feature extractor, a feature pyramid network, a first output head and a second output head. The feature extractor is configured for extracting intermediate tensors from a medical image. The feature pyramid network is associated with the feature extractor. The feature pyramid network is configured for generating multi-resolution feature maps according to the intermediate tensors. The first output head is configured for generating a global prediction according to the multi-resolution feature maps. The second output head is configured for generating local predictions according to the multi-resolution feature maps. The processor is configured to generate output information based on the medical image, the global prediction and the local predictions.

Abstract: An example computing device may include a housing having an outer panel, the outer panel comprising a first array of openings through the outer panel, an inner panel opposite the outer panel, the inner panel comprising a second array of openings and a third array of openings different than the second array of openings and an actuator to move the inner panel relative to the outer panel between (1) a first position in which the second array of openings are at least partially aligned with the first array of openings and the third array of openings are out of alignment with the first array of openings, and (2) a second position in which the third array of openings are at least partially aligned with the first array of openings and the second array of openings are out of alignment with the first array of openings.

Abstract: A datum rebuilding method is applied to a bio-sensor module equipped in a wearable electronic device with the datum rebuilding function. The datum rebuilding method includes continuously receiving a plurality of physical signals, identifying if one specific physical signal meets a predefined condition, and outputting a warning signal to show a reminder when the specific physical signal is identified.

Abstract: A datum warning method is applied to a bio-sensor module equipped in a wearable electronic device with the datum warning function. The datum warning method includes continuously receiving a plurality of physical signals, identifying if one specific physical signal meets a predefined condition, and outputting a warning signal to show a reminder when the specific physical signal is identified.

Abstract: A datum warning method and a datum rebuilding method are applied to a bio-sensor module equipped in a wearable electronic device. The wearable electronic device includes a warning interface and a bio-sensor module coupled with the warning interface. The bio-sensor module includes a sensor and a processor electrically connected with the sensor. The sensor is adapted to continuously receive a plurality of physical signal. The processor is adapted to identify if one specific physical signal meets a predefined condition, and output a warning signal to show a reminder via the warning interface when the specific physical signal is identified. Further, the processor is adapted to display each of the physical signals via the warning interface, and replace at least one of the physical signals and then store the replaced physical signal with non-replaced physical signals for rebuilding a statistic curve.

Abstract: A datum warning method and a datum rebuilding method are applied to a bio-sensor module equipped in a wearable electronic device. The wearable electronic device includes a warning interface and a bio-sensor module coupled with the warning interface. The bio-sensor module includes a sensor and a processor electrically connected with the sensor. The sensor is adapted to continuously receive a plurality of physical signal. The processor is adapted to identify if one specific physical signal meets a predefined condition, and output a warning signal to show a reminder via the warning interface when the specific physical signal is identified. Further, the processor is adapted to display each of the physical signals via the warning interface, and replace at least one of the physical signals and then store the replaced physical signal with non-replaced physical signals for rebuilding a statistic curve.

Abstract: A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer.

Abstract: A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer.