Abstract: A scaleable microprocessor architecture has an efficient and orthogonal instruction set of 20 basic instructions, and a scaleable program word size from 15 bits up, including but not limited to 16, 24, 32, and 64 bits. As many instructions are packed into a single program word as allowed by the size of a program word. An integral return stack is used for nested subroutine calls and returns. An integral data stack is also used to pass parameters among nested subroutines. The simplified instruction set and the dual stack architecture make it possible to execute all instructions in a single clock cycle from a single phase master clock. Additional instructions can be added to facilitate accessing arrays in memory, for multiplication and division of integers, for real time interrupts, and to support an UART I/O device. This scaleable microprocessor architecture greatly increases code density and processing speed while decreasing significantly silicon area and power consumption.

Abstract: A liquid-handling instrument has a worksurface with registration for modular stations to support containers of liquid, pipette apparatus with a pipette tip coupled to a sensing circuit, a robotic translation system for moving the pipette tip, and a control system with an iconic user interface for programming and editing. A gauge block registered on the worksurface provides for calibration using the sensing tip, and register cavities on the worksurface provide for modular stations. There is a wash station fop the pipette tip on the worksurface. An automated laboratory based on the liquid-handling system has heating and cooling and a sealable incubation station as well as a magnetic separation station. Methods are disclosed using the apparatus to convey droplets of liquid, to aspirate with minimum tip contamination, to mix liquids in containers, and to validate the worksurface.