Patents by Inventor Chen-Hao Chiang
Chen-Hao Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949030Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.Type: GrantFiled: March 10, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hao Chiang, Eugene I-Chun Chen, Chih-Ming Chen
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Publication number: 20230369526Abstract: A stacked (or vertically arranged) photodetector having at least one contact region on a germanium sensing region. Including the at least one contact on the germanium sensing region reduces the amount of surface area of the germanium sensing region that is interfaced with a substrate (e.g., a silicon substrate) in which the germanium sensing region is included. This reduces the amount of lattice mismatch reduces the amount of misfit defects for the germanium sensing region, which reduces the dark current for the photodetector. The reduced amount of dark current may increase the photosensitivity of the photodetector, may increase low-light performance of the photodetector, and/or may decrease noise and other defects in images and/or light captured by the photodetector, among other examples.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Chen-Hao CHIANG, Chih-Ming CHEN, Jing-Hwang YANG
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Publication number: 20230369433Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Eugene I-Chun Chen, Ru-Liang Lee, Chia-Shiung Tsai, Chen-Hao Chiang
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Patent number: 11804531Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.Type: GrantFiled: December 30, 2020Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Eugene I-Chun Chen, Ru-Liang Lee, Chia-Shiung Tsai, Chen-Hao Chiang
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Publication number: 20230299217Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.Type: ApplicationFiled: May 3, 2023Publication date: September 21, 2023Inventors: Chen-Hao Chiang, Shih-Wei Lin, Eugene I-Chun Chen, Yi-Chen Chen
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Publication number: 20230282476Abstract: In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Inventors: Lung Yuan Pan, Chen-Hao Chiang, Chih-Ming Chen
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Patent number: 11749762Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.Type: GrantFiled: June 24, 2020Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hao Chiang, Shih-Wei Lin, Eugene I-Chun Chen, Yi-Chen Chen
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Patent number: 11594606Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: GrantFiled: February 3, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Publication number: 20230033270Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.Type: ApplicationFiled: February 25, 2022Publication date: February 2, 2023Inventors: Yu-Hung Cheng, Ching I Li, Chen-Hao Chiang, Eugene I-Chun Chen, Chin-Chia Kuo
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Patent number: 11551927Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.Type: GrantFiled: November 4, 2020Date of Patent: January 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Chun Liu, Chung-Chieh Hsu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang, Min-Chang Ching
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Patent number: 11360593Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.Type: GrantFiled: July 20, 2020Date of Patent: June 14, 2022Assignee: Au Optronics CorporationInventors: Chia-Chi Lee, Sheng-Chin Fan, Che-Min Lin, Chun-Ru Huang, Chen-Hao Chiang, Yu-Hsin Hsieh, Zeng-De Chen
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Publication number: 20220131017Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.Type: ApplicationFiled: March 10, 2021Publication date: April 28, 2022Inventors: Chen-Hao Chiang, Eugene I-Chun Chen, Chih-Ming Chen
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Publication number: 20220059364Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.Type: ApplicationFiled: November 5, 2021Publication date: February 24, 2022Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
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Publication number: 20220028994Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.Type: ApplicationFiled: December 30, 2020Publication date: January 27, 2022Inventors: Eugene I-Chun Chen, Ru-Liang Lee, Chia-Shiung Tsai, Chen-Hao Chiang
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Patent number: 11171015Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.Type: GrantFiled: September 11, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen
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Publication number: 20210255722Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.Type: ApplicationFiled: July 20, 2020Publication date: August 19, 2021Applicant: Au Optronics CorporationInventors: Chia-Chi Lee, Sheng-Chin Fan, Che-Min Lin, Chun-Ru Huang, Chen-Hao Chiang, Yu-Hsin Hsieh, Zeng-De Chen
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Publication number: 20210184011Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.Type: ApplicationFiled: February 3, 2021Publication date: June 17, 2021Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
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Publication number: 20210135024Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.Type: ApplicationFiled: June 24, 2020Publication date: May 6, 2021Inventors: Chen-Hao Chiang, Shih-Wei Lin, Eugene I-Chun Chen, Yi-Chen Chen
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Patent number: 10991819Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.Type: GrantFiled: September 17, 2018Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen, Chen-Hao Chiang
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Publication number: 20210074551Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.Type: ApplicationFiled: September 11, 2019Publication date: March 11, 2021Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Alexander Kalnitsky, Yeur-Luen Tu, Eugene Chen