Abstract: A photonic device includes a silicon layer, wherein the silicon layer extends from a waveguide region of the photonic device to a device region of the photonic device, and the silicon layer includes a waveguide portion in the waveguide region. The photonic device further includes a cladding layer over the waveguide portion, wherein the device region is free of the cladding layer. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.

Abstract: A photonic device includes an optical coupler, a waveguide structure, a metal-dielectric stack, and a protection layer. The optical coupler is over a semiconductor substrate. The waveguide structure is over the semiconductor substrate and laterally connected to the optical coupler. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The protection layer lines the hole of the metal-dielectric stack.

Abstract: At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.

Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.

Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.

Abstract: A method for fabricating a photonic device is provided. The method includes patterning a semiconductor layer to form a waveguide structure, a semiconductor structure connected to the waveguide structure, and a dummy semiconductor structure disconnected from the waveguide structure and the semiconductor structure; epitaxially growing an epitaxial semiconductor feature over the semiconductor structure and a dummy epitaxial semiconductor feature over the dummy semiconductor structure; depositing a first capping film over the epitaxial semiconductor feature and the dummy epitaxial semiconductor feature; depositing a second capping film over the first capping film, wherein an oxide concentration of the second capping film is greater than an oxide concentration of the first capping film; and patterning the first and second capping films to form at least a dummy composite capping layer over the dummy epitaxial semiconductor feature.

Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.

Abstract: This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC.

Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.

Abstract: This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC.

Abstract: A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.

Abstract: A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.

Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Abstract: A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.

Abstract: A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons are accelerated by a depletion region established by a voltage applied to a source region and a drain region, and a vertical electrical field established between a control gate and the P-type well region further forces the electrons to be injected into a charge storage layer. Since the present invention adopts the substrate hot carrier effect to inject carriers into the charge storage layer, the required program operation voltage is low, which benefits to save power consumption and enhance the reliability of the device.