Abstract: A light-emitting module includes a light guide member, a first reflective paint layer, a first light-absorbing paint layer, a circuit board, and a light-emitting unit. The light guide member includes a positioning surface, a first side surface, a second side surface, and a light emergence surface. The positioning surface includes a groove. The first reflective paint layer is arranged on the first side surface, and the first light-absorbing paint layer is arranged on the first reflective paint layer. The circuit board is located on the positioning surface. The light-emitting unit is arranged on the circuit board and is accommodated in the groove. In this way, the light-emitting unit on the circuit board may change a light path and project light to the light emergence surface, thereby reducing a required stack thickness of the light-emitting module.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: An optical beam splitter includes a multi-stage nested network of waveguide bifurcation branches, which includes: first-stage waveguide bifurcation branches each including a pair of first-stage waveguide segments, and second-stage waveguide bifurcation branches each including a pair of second-stage waveguide segments. Each pair of first-stage waveguide segments includes a first common end and a pair of first split ends and a pair of first interconnection portions. Each first common end points toward a first widthwise direction. Each pair of second-stage waveguide segments includes a second common end and a pair of second split ends and a pair of second interconnection portions. Each second common end and each second split end of the optical beam splitter point toward a second widthwise direction which is an opposite direction of the first widthwise direction.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

Abstract: An antenna structure capable of transmitting a WiGig band for a head-mounted wireless transmission display device including a display screen and an overhead device is disclosed. The antenna structure includes at least two body portions, each of the body portions having at least a signal transceiving end, the body portions are respectively arranged at left and right sides of the display screen, and signal transceiving ends of the body portions are extended outward from the left and right sides of the display screen respectively.

Abstract: A co-packaged structure for optics and electrics includes a substrate, an optical module and an electrical connection layer. The optical module includes a carrier and an optical transceiver unit. The carrier is mounted on the substrate. The optical module is mounted on the carrier. The electrical connection layer is mounted on the substrate, and the carrier is electrically connected with a circuitry on the substrate through the electrical connection layer. A plurality of fiber accommodation through hole are formed on the substrate and correspond to the optical transceiver unit.

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.

Abstract: A light-emitting diode package includes a redistribution layer, a light-emitting diode, a first dielectric layer, a plurality of wavelength conversion structures, and a transparent encapsulant. The light-emitting diode is disposed on and electrically connected to the redistribution layer. The light-emitting diode includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first dielectric layer is disposed on the redistribution layer and covers the light-emitting diode. The wavelength conversion structures are disposed on the first dielectric layer and respectively in contact with the second light-emitting diode and the third light-emitting diode. The transparent encapsulant is disposed on the first dielectric layer and covers the plurality of wavelength conversion structures. In addition, a manufacturing method of the light-emitting diode package is provided.

Abstract: A method for forming resistance on circuit board is provided and includes the following steps. First, a substrate is provided. Next, a second metal layer is provided on the substrate, and the first metal layer is covered by the second metal layer. Then, a resistance is formed on the second metal layer, and the resistance is directly above the first metal layer. Thereafter, the second metal layer is cut so that the edge of the second metal layer is aligned with that of the first metal layer. The second metal layer is separated from the first metal layer. Next, the second metal layer is pressed with a circuit board, and the resistance is attached to a dielectric layer of the circuit board. Then, the second metal layer is etched to form a circuit pattern on the resistance.

Abstract: A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.

Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.