Patents by Inventor Chen-Hsi Lin
Chen-Hsi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 10483235Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.Type: GrantFiled: March 1, 2016Date of Patent: November 19, 2019Assignee: WINBOND ELECTRONICS CORP.Inventors: Yu-Cheng Chiao, Tung-Yi Chan, Chen-Hsi Lin, Chia Hua Ho, Meng-Chang Chan, Hsin-Hung Chou
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Patent number: 9881901Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.Type: GrantFiled: February 4, 2016Date of Patent: January 30, 2018Assignee: WINBOND ELECTRONICS CORP.Inventors: Yu-Cheng Chiao, Tung-Yi Chan, Chen-Hsi Lin, Chia Hua Ho, Meng-Chang Chan, Hsin-Hung Chou
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Publication number: 20160329244Abstract: A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.Type: ApplicationFiled: March 1, 2016Publication date: November 10, 2016Inventors: Yu-Cheng CHIAO, Tung-Yi CHAN, Chen-Hsi LIN, Chia Hua HO, Meng-Chang CHAN, Hsin-Hung CHOU
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Publication number: 20160329305Abstract: A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality of first bonding pads, and the second substrate includes a plurality of second bonding pads. A three-dimensional (3D) printing is performed to form an encapsulating layer covering the first substrate and the second substrate and to form a plurality of bonding wires in the encapsulating layer. Each bonding wire includes a first portion connected to one of the plurality of first bonding pads. The disclosure also provides a stacked package device formed by such a method.Type: ApplicationFiled: February 4, 2016Publication date: November 10, 2016Inventors: YU-CHENG CHIAO, TUNG-YI CHAN, CHEN-HSI LIN, CHIA HUA HO, MENG-CHANG CHAN, HSIN-HUNG CHOU
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Patent number: 6026028Abstract: A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.Type: GrantFiled: July 28, 1998Date of Patent: February 15, 2000Assignee: Worldwide Semiconductor Manufacturing Corp.Inventors: Chen-Hsi Lin, Chih-Ming Chen, Ling-Sung Wang, Horng-Ming Lee, Ko-Hsing Chang
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Patent number: 5668065Abstract: A process for simultaneously forming a self-aligned contact, a local interconnect and a self-aligned silicide in a semiconductor device. An oxide layer is deposited over a gate structure, a source region and a drain region formed on a substrate of the semiconductor device. The gate structure may be a multi-layer structure including a polysilicon gate, a silicon nitride layer and a tungsten silicide layer. The oxide layer deposited over the gate, source and drain is etched to define portions of the oxide layer which will form contact areas of a self-aligned contact and a local interconnect of the semiconductor device. An amorphous silicon layer is then deposited over the etched oxide layer to a thickness selected such that substantially the entire thickness of remaining portions of the amorphous silicon layer will be consumed during a subsequent silicidation reaction.Type: GrantFiled: August 1, 1996Date of Patent: September 16, 1997Assignee: Winbond Electronics Corp.Inventor: Chen-Hsi Lin
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Patent number: 5476800Abstract: The present invention provides a buried layer fabrication sequence suitable for bipolar and BiCMOS applications. The buried layer fabrication sequence for forming a buried layer having a first conductivity type includes the steps of: forming a first dielectric layer on a semiconductor substrate, the semiconductor substrate having a second conductivity type; forming a first mask layer having openings on top of the first dielectric layer, wherein the openings in the first mask layer are positioned over the regions where the first buried layer is formed; exposing the semiconductor substrate in the regions where openings in the first mask layer are formed; forming a second dielectric layer; removing the second dielectric layer; and forming a semiconductor layer.Type: GrantFiled: January 31, 1994Date of Patent: December 19, 1995Inventors: Gregory N. Burton, Chen-Hsi Lin, Chi-Kwan Lau
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Patent number: 5158900Abstract: A method of fabricating a BiCMOS device in which PMOS and NMOS transistors are formed prior to a base/emitter structure of a bipolar transistor. In forming the base/emitter structure, a blanket implant of a first impurity is introduced into a base region of a semiconductor substrate. An insulating layer is deposited and then patterned to expose a portion of the base region at an emitter window. A polysilicon layer is deposited on the insulating layer and into the emitter window. The polysilicon layer is patterned to provide the desired configuration at the emitter window, whereafter the remaining polysilicon acts as a mask for etching of the insulating layer. Thus, etching of the insulating layer is performed in a self-aligning manner. Self-alignment is also utilized in providing a base-link region and in providing a silicide layer.Type: GrantFiled: October 18, 1991Date of Patent: October 27, 1992Assignee: Hewlett-Packard CompanyInventors: Chi-Kwan Lau, Donald L. Packwood, Chen-Hsi Lin, Ashor Kapoor
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Patent number: 5108542Abstract: A method of plasma etching tungsten containing films such as is found in semiconductor interconnects. The etch method is conducted under reactive ion etch conditions in a plasma etch reactor using a gas mixture of CF.sub.4 and O.sub.2. The O.sub.2 preferably makes up 20% to 60% of the gas mixture by volume. The etch method is highly selective to titanium disilicide, titanium nitride and silicon dioxide.Type: GrantFiled: August 23, 1990Date of Patent: April 28, 1992Assignee: Hewlett Packard CompanyInventor: Chen-Hsi Lin