Patents by Inventor Chen-Hsiang Hsieh
Chen-Hsiang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11942652Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.Type: GrantFiled: April 13, 2022Date of Patent: March 26, 2024Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
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Patent number: 11929016Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.Type: GrantFiled: December 5, 2022Date of Patent: March 12, 2024Assignee: MACROBLOCK, INC.Inventors: Chi-Min Hsieh, Che-Wei Chang, Chen-Yuan Kuo, Wei-Hsiang Cheng
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Patent number: 10461723Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.Type: GrantFiled: November 30, 2017Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsien Tsai, Chen-Hsiang Hsieh, Ruey-Bin Sheen, Chih-Hsien Chang
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Publication number: 20190165769Abstract: A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Tsung-Hsien TSAI, Chen-Hsiang Hsieh, Ruey-Bin SHEEN, Chih-Hsien CHANG
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Patent number: 6629450Abstract: A method for automatically conducting a leak test for a vacuum system includes receiving a process status input representing the completion of a manufacturing cycle. On determining that the process status is in a complete state, the vacuum system isolation valve is closed. In one embodiment, the first pressure input is measured at the beginning of the leak test and compared to a second pressure input measured at the expiration of timer. If the difference between the first and second pressure measurements are greater than the configurable threshold pressure, then the vacuum system is determined to be leaky. In another embodiment, the vacuum system is determined to be leaky if at least one of a series of pressure measurements exceeds the threshold pressure value. In response to the determination of the leak, an interlock signal to disable the operation of the vacuum system is activated.Type: GrantFiled: July 13, 2001Date of Patent: October 7, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hsueh-Chin Lu, Min-Je Chiang, Chen-Hsiang Hsieh
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Publication number: 20030010092Abstract: A method for automatically conducting a leak test for a vacuum system includes receiving a process status input representing the completion of a manufacturing cycle. On determining that the process status is in a complete state, the vacuum system isolation valve is closed. In one embodiment, the first pressure input is measured at the beginning of the leak test and compared to a second pressure input measured at the expiration of timer. If the difference between the first and second pressure measurements are greater than the configurable threshold pressure, then the vacuum system is determined to be leaky. In another embodiment, the vacuum system is determined to be leaky if at least one of a series of pressure measurements exceeds the threshold pressure value. In response to the determination of the leak, an interlock signal to disable the operation of the vacuum system is activated.Type: ApplicationFiled: July 13, 2001Publication date: January 16, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chin Lu, Min-Je Chiang, Chen-Hsiang Hsieh