Abstract: A wireless communication system and related wireless devices are disclosed. The wireless communication system includes: a source wireless device configured to operably insert an auto-pairing request and one or more source Bluetooth device addresses into one or more predetermined advertising packets to form one or more target advertising packets, and configured to operably transmit the target advertising packets; and a destination wireless device configured to operably receive and parser the target advertising packets to extract the auto-pairing request and the one or more source Bluetooth device addresses. The destination wireless device performs an auto-pairing procedure with the source wireless device according to the auto-pairing request and the one or more source Bluetooth device addresses to establish a Bluetooth bond with the source wireless device.

Abstract: A Bluetooth service estimation apparatus and a Bluetooth service estimation method thereof are provided. The Bluetooth service estimation apparatus listens to data packets transmitted between the Bluetooth host and the remote Bluetooth device, and determines a Bluetooth service type between the Bluetooth host and the remote Bluetooth device according to contents of the data packets. The Bluetooth service estimation apparatus transmits the Bluetooth service type to a packet traffic arbitration module of a Wi-Fi host so that the Wi-Fi host determines a weight of network resources according to the Bluetooth service type, and decides a utilization rate of an antenna based on the weight of the network resources.

Abstract: A wireless communication system and related wireless devices are disclosed. The wireless communication system includes: a source wireless device configured to operably insert an auto-pairing request and one or more source Bluetooth device addresses into one or more predetermined advertising packets to form one or more target advertising packets, and configured to operably transmit the target advertising packets; and a destination wireless device configured to operably receive and parser the target advertising packets to extract the auto-pairing request and the one or more source Bluetooth device addresses. The destination wireless device performs an auto-pairing procedure with the source wireless device according to the auto-pairing request and the one or more source Bluetooth device addresses to establish a Bluetooth bond with the source wireless device.

Abstract: A Bluetooth remote control system and related transmitting-end Bluetooth device and receiving-end Bluetooth device are disclosed. The transmitting-end Bluetooth device includes: a Bluetooth transmitting circuit; a receiving interface configured to operably receive a user trigger signal; a packet generating circuit configured to operably insert a power on request into one or more predetermined advertising packets to form one or more target advertising packets; and a Bluetooth control circuit configured to operably control the Bluetooth transmitting circuit to transmit the one or more target advertising packets. Each of the predetermined advertising packets is an advertising indication (ADV_IND) packet, a non-connectable advertising indication (ADV_NONCONN_IND) packet, or a discoverable advertisement indication (ADV_DISCOVER_IND) packet.

Abstract: A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.

Abstract: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.

Abstract: A Bluetooth service estimation apparatus and a Bluetooth service estimation method thereof are provided. The Bluetooth service estimation apparatus listens to data packets transmitted between the Bluetooth host and the remote Bluetooth device, and determines a Bluetooth service type between the Bluetooth host and the remote Bluetooth device according to contents of the data packets. The Bluetooth service estimation apparatus transmits the Bluetooth service type to a packet traffic arbitration module of a Wi-Fi host so that the Wi-Fi host determines a weight of network resources according to the Bluetooth service type, and decides a utilization rate of an antenna based on the weight of the network resources.

Abstract: A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region.

Abstract: A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points.

Abstract: A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule.

Abstract: A congestive placement preventing apparatus, applied in a logic circuit layout having 2K logic circuits, where K is a positive integer, is provided. The congestive placement preventing apparatus includes a restructuring module and a synthesizing module. The restructuring module adds a selecting unit in the logic circuit layout, and adds (N?K) buffers in each of the 2K logic circuits, where N is a positive integer. The synthesizing module synthesizes the restructured logic circuit layout according to a plurality of “don't touch” synthesizing commands associated with the added buffers. In the synthesized logic circuit layout, all of the 2K logic circuits are independent and not coupled or merged with one another.

Abstract: An apparatus of preventing congestive placement is provided. The apparatus comprises a judging module, a pattern generating module, and a placement module. The judging module judges whether a circuit layout comprises a congestive region according to a judging rule. When a judgment result of the judging module is affirmative, the pattern generating module generates a redistribution pattern with a density distribution of blockages. The density distribution gradually decreases outward. The placement module regards the congestive region as the center redistributes the blockages and electronic cells according to the redistribution pattern.

Abstract: A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region.

Abstract: A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.

Abstract: A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule.

Abstract: A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-dimensional interface arrangement to a one-dimensional interface arrangement according to the conversion rate, forming a one-dimensional clock tree according to the one-dimensional interface arrangement, generating the clock tree corresponding to the two-dimensional interface arrangement by converting the one-dimensional clock tree according to the conversion rate.

Abstract: A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface.

Abstract: A change point finding method applied to a logic circuit is provided. The method first defines an indication map and performs a functional equivalent check to judge whether the indication map is correct. When a result is confirmative, the method adds a trap to an RTL HDL of the logic circuit, so that a plurality of comparing points are generated in an APR gate level HDL of the logic circuit. Then the method performs a backward functional equivalent check on the APR gate level HDL of the logic circuit to find a change point according to the comparing points.

Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.

Abstract: A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip.