Patents by Inventor Chen-Hsuan Chiu

Chen-Hsuan Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor devices with co-coupling electrode planes
    Patent number: 8125761
    Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Chen-Hsuan Chiu
  • ESD protection structure
    Patent number: 7894172
    Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 22, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Liang Pan, Min-Lin Lee, Shinn-Juh Lai, Shih-Hsien Wu, Chen-Hsuan Chiu
  • ESD protection substrate and integrated circuit utilizing the same
    Patent number: 7649723
    Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: January 19, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Hsuan Chiu, Min-Lin Lee, Shinn-Juh Lai, Shih-Hsien Wu, Chi-Liang Pan
  • CAPACITOR DEVICES WITH CO-COUPLING ELECTRODE PLANES
    Publication number: 20090213526
    Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 27, 2009
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Chen-Hsuan Chiu
  • ESD PROTECTION STRUCTURE
    Publication number: 20090180225
    Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.
    Type: Application
    Filed: August 13, 2008
    Publication date: July 16, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Liang Pan, Min-Lin Lee, Shinn-Juh Lai, Shih-Hsien Wu, Chen-Hsuan Chiu
  • ESD PROTECTION SUBSTRATE AND INTEGRATED CIRCUIT UTILIZING THE SAME
    Publication number: 20090097175
    Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.
    Type: Application
    Filed: March 12, 2008
    Publication date: April 16, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chen-Hsuan Chiu, Min-Lin Lee, Shinn-Juh Lai, Shih-Hsien Wu, Chi-Liang Pan