Patents by Inventor Chen-Hsuan Tsai

Chen-Hsuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118642
    Abstract: A method of forming a semiconductor package includes the following operations. At least one integrated circuit structure is provided and bonded to an interposer structure. A photonic structure is provided and bonded to the interposer structure, wherein the photonic structure has a recessed feature covered by a mask and facing a light source. An encapsulation layer is formed around the at least one integrated circuit structure and the photonic structure. At least a portion of the mask layer is removed from the photonic structure.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang
  • Patent number: 12272568
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240395772
    Abstract: A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.
    Type: Application
    Filed: May 28, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Ying-Ching Shih
  • Publication number: 20240395730
    Abstract: A package includes a first die and a second die in an encapsulant layer, and a dummy bar in the encapsulant layer and adjacent a gap between the first die and the second die. A method of forming a package includes attaching a first die and a second die to a surface, attaching a dummy bar to the surface adjacent a gap between the first die and the second die, and forming an encapsulant layer on the first die, the second die and the dummy bar.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Ching-Chen Li, Chin-Chuan Chang, Chen-Hsuan Tsai
  • Publication number: 20240387197
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Patent number: 12142579
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. At least one of the reinforcement pattern layers is embedded in the insulating encapsulation. The reinforcement structure is electrically floating.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Publication number: 20240304466
    Abstract: A method of fabricating a semiconductor device is provided. The method includes providing a die stacking unit that includes a plurality of dies stacked on each other, and a plurality of conductive joints connected between each two adjacent dies. The method includes providing a plurality of dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. The method includes dispensing an underfill material into gaps between the plurality of dies, the conductive joints, the dummy micro bumps, and the dummy pads.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: Tsung-Fu TSAI, Chen-Hsuan TSAI, Chung-Chieh TING, Shih-Ting LIN, Szu-Wei LU
  • Publication number: 20240282713
    Abstract: A package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. The first redistribution circuit structure has a first side and a second side opposite to the first side. The first semiconductor die is disposed over the firs side of the first redistribution circuit structure. The second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. A material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Yu-Lin CHIANG, Chin-Chuan Chang, Ying-Ching Shih
  • Patent number: 12020952
    Abstract: A method of fabricating a semiconductor device is provided, including providing a base substrate and a die stacking unit mounted on the base substrate. Conductive joints are connected between two adjacent dies of the die stacking unit. The method further includes providing dummy micro bumps and dummy pads between the two adjacent dies and between the conductive joints. The dummy micro bumps and the dummy pads are connected to one of the two adjacent dies but not to the other, and the dummy micro bumps are formed on some of the dummy pads but not on all of the dummy pads. In addition, the method includes filling the gaps between the base substrate, all dies of the die stacking unit, the conductive joints, the dummy micro bumps, and the dummy pads with an underfill material by capillary attraction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Fu Tsai, Chen-Hsuan Tsai, Chung-Chieh Ting, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11990351
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240105629
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Publication number: 20240071849
    Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20240055410
    Abstract: A package structure is provided. The package structure includes a substrate and a semiconductor chip over the substrate. The package structure also includes a protective frame laterally surrounding the semiconductor chip. The package structure further includes an underfill element between the semiconductor chip and the protective frame. A portion of the underfill element is directly below the protective frame.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 15, 2024
    Inventors: Chen-Hsuan TSAI, Tsung-Fu TSAI, Shih-Ting LIN, Szu-Wei LU
  • Publication number: 20240021442
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: August 1, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai
  • Publication number: 20240021491
    Abstract: A semiconductor device includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die includes a conductive paste on a first surface of the first integrated circuit die, wherein the conductive paste is in direct contact with the first surface of the first integrated circuit die. The second integrated circuit die is disposed aside the first integrated circuit die, wherein a surface of the conductive paste is substantially coplanar with a surface of the second integrated circuit die.
    Type: Application
    Filed: July 17, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Hung-Chih Chen, Chin-Chuan Chang
  • Patent number: 11854984
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11817425
    Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20230361052
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. At least one of the reinforcement pattern layers is embedded in the insulating encapsulation. The reinforcement structure is electrically floating.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Patent number: 11769739
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has dielectric layers. The wiring substrate is disposed on the redistribution circuit structure. The semiconductor device is disposed on the redistribution circuit structure opposite to the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is partially embedded in the redistribution circuit structure and is partially embedded in the insulating encapsulation. The reinforcement structure includes reinforcement pattern layers and reinforcement vias. The reinforcement pattern layers and the dielectric layers are stacked alternately. The reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers. The reinforcement structure is electrically floating.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Publication number: 20220310411
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ting Chen, Chih-Wei Wu, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih, Ting-Yu Yeh, Chen-Hsuan Tsai