Patents by Inventor Chen-Hua Cheng

Chen-Hua Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961791
    Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
  • Publication number: 20240071965
    Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Tung-Liang Shao, Yu-Sheng Huang, Wen-Hao Cheng, Chen-Hua Yu
  • Patent number: 11562972
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 24, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Patent number: 11540396
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 27, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Publication number: 20220071000
    Abstract: The disclosure provides a circuit board structure including at least two sub-circuit boards and at least one connector. Each of the sub-circuit boards includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.
    Type: Application
    Filed: January 14, 2021
    Publication date: March 3, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Publication number: 20220071015
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 3, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Publication number: 20210398925
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Patent number: 11145610
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 12, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Publication number: 20210202407
    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Yu-Chi Shen, Tzyy-Jang Tseng, Chen-Hua Cheng, Pei-Wei Wang
  • Publication number: 20190296102
    Abstract: An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads.
    Type: Application
    Filed: September 27, 2018
    Publication date: September 26, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Chen-Hua Cheng, Chin-Sheng Wang, Chung-Chi Huang
  • Publication number: 20070293340
    Abstract: An adjustable stick-like sport apparatus has an outer tube and a stick, the outer tube has an opening. The stick slidably mounted in the outer tube and has an extension portion formed in one end and inserted into the outer tube. Two nipping members encircle the extension portion, are engaged with the extension portion and are mounted slidably in the outer tube. When the user rotates the stick with the extension portion, the nipping members are stable relative to the extension portion. The sticks may extend out of or retract in the outer tube to vary a length of the adjustable stick-like sport apparatus. After the length is adjusted, reversely rotating the stick causes the two nipping members to tightly abut the outer tube to fix the length of the adjustable stick-like sport apparatus.
    Type: Application
    Filed: June 17, 2006
    Publication date: December 20, 2007
    Inventor: Chen-Hua Cheng
  • Patent number: 7261654
    Abstract: An extendable bat has a covering member, a tubular core, a handle, an adjusting device, a cap, and a collar. The adjusting device has a first locking member and a second locking member. With the cooperation of the first locking member and the second locking member, the length of the bat can be adjusted and the handle is held in place at a desired length. Accordingly, the cost for manufacturing the extendable bat is lowered.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: August 28, 2007
    Inventor: Chen-Hua Cheng
  • Publication number: 20070142135
    Abstract: An extendable bat has a covering member, a tubular core, a handle, an adjusting device, a cap, and a collar. The adjusting device has a first locking member and a second locking member. With the cooperation of the first locking member and the second locking member, the length of the bat can be adjusted and the handle is held in place at a desired length. Accordingly, the cost for manufacturing the extendable bat is lowered.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventor: Chen-Hua Cheng
  • Publication number: 20060037216
    Abstract: A boot for a skate has a shoe frame and a shoe sheath. The shoe frame has a heel shank and an insole. The shoe sheath is mounted on the shoe frame and has a sidewall, an internal soft pad and a leather upper cover. The sidewall has an internal chamber. The internal soft pad is made of resilient material and has multiple air vents defined through the internal soft pad. The air vents improve the ventilation of the sidewall to make a sole of a foot inside the sidewall feel comfortable without sweating easily and also keep the sole from becoming unhealthy.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 23, 2006
    Inventors: Chen-Hua Cheng, Ye-Hua Lin Liao
  • Patent number: 6057601
    Abstract: The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached. The IC wire bonds within the cavity are sealed with an organic encapsulant.
    Type: Grant
    Filed: November 27, 1998
    Date of Patent: May 2, 2000
    Assignee: Express Packaging Systems, Inc.
    Inventors: John H. Lau, Tzyy Jang Tseng, Chen-Hua Cheng