Abstract: A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier metallization layer has formed in-situ upon its surface a silicon layer. The silicon layer has a thickness such that the contact resistance of the barrier metallization layer is not substantially increased. In a further embodiment, the barrier metallization layer and the silicon layer are sintered to form a metal silicide layer upon the surface of the barrier metallization layer.

Abstract: An improvement in the properties of etch rate, mechanical stress, and chemical resistance of silicon layers obtained by plasma-enhanced chemical vapor deposition from mixtures of reactive gases such as oxygen and tetraethoxysilane is achieved by adding nitrogen gas to the reactive gas mixture. The addition of nitrogen gas is effective in improving the cited properties of the silicon oxide layers without altering the basic properties of the deposition process or degrading the other desirable properties of the silicon oxide layers in any substantial manner.

Abstract: A method of field oxide formation which creates field oxides of comparatively uniform height between differently-spaced oxidation masks is disclosed. A patterned oxidation mask, typically silicon nitride, (possibly with underlying polysilicon) is formed. A blanket layer of polysilicon is formed and etched back, thereby filling spaces between closely-spaced portions of the oxidation mask and fillets between less-closely spaced portions. A thermal oxidation is performed to produce a field oxide. The field oxide has comparatively uniform height despite differences in oxidation mask spacing.

Abstract: An integrated circuit is described which has an electrical contact formed between a metallic silicide and .alpha.:Si. The method of integrated circuit manufacturing comprising the steps of: forming a layer of a metallic silicide; depositing a layer of .alpha.:Si on said metallic silicide at a temperature less than the recrystallization temperature; and increasing the conductivity of at least selected portions of said .alpha.:Si by ion implanting a species having the peak of its spatial distribution spaced from the .alpha.:Si-Silicide interface and the .alpha.:Si surface.

Abstract: An interlevel dielectric comprised of phosphorus-doped glass surrounding the second polysilicon level of an SRAM cell is disclosed. The second polysilicon is generally a cell local interconnect. The phosphorus-doped glass layer efficiently getters sodium from underlying layers. The phosphorus-doped glass layer is utilized although another doped gettering layer may be used at a higher level of the circuit.

Abstract: A method for forming a narrow cross-sectional diameter via through an insulator layer for use within an integrated circuit. Formed upon a semiconductor substrate is a metal layer. At least the top surface of the metal layer is formed from a titanium nitride layer. Formed upon the titanium nitride layer is an insulator layer. The insulator layer exhibits a first incubation time with respect to forming an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the insulator layer. The first incubation time is less than a second incubation time for forming the same ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator coating upon the titanium nitride layer. A conventional via is then formed completely through the insulator layer. The bottom of the conventional via exposes a portion of the titanium nitride layer.

Abstract: A semiconductor integrated circuit, and process for its manufacture, are disclosed which contains both n.sup.+ and p.sup.+ gates that do not pose a risk of dopant interdiffusion. Both n.sup.+ and p.sup.+ gates may be fabricated by conventional means. The gate structures are severed over the tub boundaries. A titanium nitride interconnective layer is deposited and patterned over the gates. The interconnective layer preserves connectivity between the n.sup.+ and p.sup.+ gates without risk of deleterious dopant interdiffusion.

Abstract: A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated intergrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

Abstract: A method for forming transistors having sublithographic features, for example, gates, is disclosed. A patterned hardmask (formed, for example from PETEOS) is created overlying oxide and polysilicon layers. The dimensions of the hardmask are reduced by isotropic etching. The reduced-dimension hardmask is used with an anisotropic etching process to define a reduced-dimension feature such as a gate.

Abstract: A method of fabricating integrated circuits is disclosed. A layer of doped silicon dioxide is deposited over a partially fabricated integrated circuit. The doped silicon dioxide is heated to permit it to attract sodium ions. After the doped silicon dioxide has been heated, it is removed by an etching process which exhibits great selectivity to the remaining underlying portion of the integrated circuit.

Abstract: A method of semiconductor integrated circuit fabrication including a technique for forming punch-through control implants is disclosed. After gate formation, a dielectric is formed which covers the gate and exposed portions of a semiconductor substrate. The dielectric is formed by a process which makes that portion of the dielectric adjacent the gate sidewalls more vulnerable to wet etching than those portions of the dielectric which are adjacent the top of the gate and the exposed substrate. The dielectric is then subsequently etched to form channels adjacent the gate which exposed the substrate and served to collimate an ion implantation beam. The remaining portions of the dielectric may then be stripped away and conventional procedures employed to form source and drain. Illustratively, the dielectric is formed from TEOS to which NF.sub.3 is added during the deposition process. The addition of NF.sub.

Abstract: A method for forming a twin tub semiconductor integrated circuit is disclosed. A portion of a semiconductor substrate is masked by oxide, nitride and photoresist. P-type dopant is directed towards the other portion of the substrate. Subsequently, the photoresist is removed and a protective oxide is grown over the p-tub, thereby driving the dopant into the substrate. Next, an n-type ion implantation is performed to create the n-tub. The n-type ions are directed at the substrate at an angle which is away from normal incidence. The angular direction of the n-type dopants permits the use of smaller screen oxides over the n-tub and smaller protective oxides over the already-formed p-tub. When all of the protective oxides have been removed, the inventive technique provides a twin tub substrate having a comparatively smooth upper surface.

Abstract: A method of semiconductor integrated circuit fabrication which provides a tapered window and a smoothed dielectric. A trench is made by etching through patterned photoresist into a dielectric. Then the corners of the trench are smoothed by thermal flow. Next the trench is etched downward by RIE blanket etchback. A window with tapered sides is thereby opened to the substrate and the dielectric is simultaneously smoothed.

Abstract: A workpiece is formed comprising a silicon substrate covered by four successive layers of silicon dioxide, undoped polysilicon, undoped WSi.sub.2 and a top layer of silicon dioxide on silicon nitride. The four layers are patterned to provide gate electrode structures each comprising the four layers. The workpiece is covered with a masking layer and the top layer of each structure is exposed through the masking layer. The top layers are then removed and ions of one conductivity type are implanted into the WSi.sub.2 layers of one group of gate electrode structures while another group of structures is masked, and ions of the other conductivity type are implanted into the WSi.sub.2 layers of the second group while the first group is masked. Thereafter, doped regions are formed in the substrate adjacent to the gate electrode structures.

Abstract: A method of forming a planarized or smoothed dielectric or other material layer upon a partially fabricated integrated circuit is disclosed. Conventional planarization techniques involve deposition of a dielectric or other material layer followed by anisotropic etchback. Unfortunately, some commercial equipment tends to etch the center of the wafer faster than the edges. The disclosed process forms a layer which is thicker in the central region than the edge region. Thus, when the disclosed process is followed by a conventional etchback, a planar dielectric or other material layer over the entire wafer is formed. Other aspects of the invention include processes and apparatus for producing smooth deposition and etching by control of the impedance of the etching and/or chemical precursor gases.

Abstract: A method for anisotropically depositing a dielectric from a precursor gas in a reactor is disclosed. The method includes reduced pressure, reduced oxygen/precursor gas flow ratio, increased spacing between shower head and susceptor; and also a susceptor having a diameter greater than the diameter of the wafer.

Abstract: In the manufacture of integrated circuits, a process for forming a dielectric layer such as silicon dioxide which has a high wet etch rate is disclosed. Illustratively, the process is performed with a precursor gas in a plasma reactor with a shower head and a susceptor which supports a wafer. The power density, pressure, susceptor-shower head spacing, and (optionally) temperature are respectively decreased, decreased, increased and decreased to reduce the effectiveness of dissociation of the precursor gas. The resulting film contains impurities which enhance its wet etch rate.

Abstract: A method of forming p.sup.+ transistor gates is disclosed. A polysilicon layer is covered with an amorphous silicide layer which prevents penetration of p-type dopants through the gate oxide. The silicide may be covered by a dielectric which is formed at a temperature low enough to prevent crystallization of the silicide, a p-type dopant species is directed at the silicide layer. Subsequently an anneal is performed at a temperature high enough to cause a substantial amount of the p-type dopant to move to the polysilicon layer.

Abstract: A method for forming a thin high quality interlevel dielectric is disclosed. The dielectric is produced in a plasma reactor utilizing a precursor gas such as TEOS. Pressure, power, temperature, gas flow, and showerhead spacing are controlled so that a dielectric of TEOS may be deposited at 60-5 .ANG. / sec, thus making formation of thin (800 .ANG.) high quality dielectrics feasible.

Abstract: A process for removing both the silicon nitride layer and polysilicon layer in a poly-buffered LOCOS process which utilizes hot phosphoric acid is disclosed.