Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: In some examples, a method for conditioning a wafer processing chamber comprises setting a pressure in the chamber to a predetermined pressure range, setting a temperature of the chamber to a predetermined temperature, and supplying a process gas mixture to a gas distribution device within the chamber. A plasma is struck within the chamber and a condition in the chamber is monitored. Based on a detection of the monitored condition meeting or transgressing a threshold value, a chamber conditioning operation is implemented. The chamber conditioning operation may include depositing a preconditioning film onto an internal surface of the chamber, depositing a silicon oxycarbide (SiCO) film onto the preconditioning film, and depositing a protective layer onto the SiCO film.

Abstract: In some examples, a method for conditioning a wafer processing chamber comprises setting a pressure in the chamber to a predetermined pressure range, setting a temperature of the chamber to a predetermined temperature, and supplying a process gas mixture to a gas distribution device within the chamber. A plasma is struck within the chamber and a condition in the chamber is monitored. Based on a detection of the monitored condition meeting or transgressing a threshold value, a chamber conditioning operation is implemented. The chamber conditioning operation may include depositing a preconditioning film onto an internal surface of the chamber, depositing a silicon oxycarbide (SiCO) film onto the preconditioning film, and depositing a protective layer onto the SiCO film.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: In some examples, a method for conditioning a wafer processing chamber comprises setting a pressure in the chamber to a predetermined pressure range, setting a temperature of the chamber to a predetermined temperature, and supplying a process gas mixture to a gas distribution device within the chamber. A plasma is struck within the chamber and a condition in the chamber is monitored. Based on a detection of the monitored condition meeting or transgressing a threshold value, a chamber conditioning operation is implemented. The chamber conditioning operation may include depositing a preconditioning film onto an internal surface of the chamber, depositing a silicon oxycarbide (SiCO) film onto the preconditioning film, and depositing a protective layer onto the SiCO film.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Forming a protective coating ex situ in an atomic layer deposition process to coat one or more chamber components subsequently installed in a reaction chamber provides a number of benefits over more conventional coating methods such as in situ deposition of an undercoat. In certain cases the protective coating may have a particular composition such as aluminum oxide, aluminum fluoride, aluminum nitride, yttrium oxide, and/or yttrium fluoride. The protective coating may help reduce contamination on wafers processed using the coated chamber component. Further, the protective coating may act to stabilize the processing conditions within the reaction chamber, thereby achieving very stable/uniform processing results over the course of processing many batches of wafers, and minimizing radical loss. Also described are a number of techniques that may be used to restore the protective coating after the coated chamber component is used to process semiconductor wafers.

Abstract: Electrical stimulation system and method for generating virtual channels are disclosed. The electrical stimulation system comprises: an electrode controller, a carrier, a plurality of electrode units, and a buffer layer. The electrode units are disposed on the carrier, and each of the electrode units are electrically connected to the electrode controller independently. Besides, the electrode units and the carrier are covered with the buffer layer. When the electrode controller receive a control signal and drive the corresponding electrode units, the electrical currents output from the corresponding electrode units can electrically interfere with each other to generate a virtual channel between the corresponding electrode units.

Abstract: A 5.1 channel signal output mixer circuit for earphone using step gain amplification unit comprising a filtering gain unit, a mixing gain unit and a noise reduction gain unit, wherein said filtering gain unit obtaining a bandwidth-adjusted subwoofer signal from two waveform shaping circuits, said mixing gain mixing said subwoofer signal with an output signal of a front channel to form a first signal, said noise reduction gain receiving said first signal for noise removal to form a signal and outputting said signal to a speaker.