Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A frequency-variation type demodulator and demodulating method. A start signal is received by a control signal apparatus. After a delay time, a control signal is output. The control signal, a start frequency, a frequency variation slope and a clock are received by an in-phase and quadrature-phase function generator. A phase value is output via mathematical calculation. According to the phase value, a cosine and sine values are obtain by checking a phase look-up table in a first and a second ROM units, respectively. The cosine value is multiplied by a measured digital data in a first multiplier to obtain an in-phase demodulating signal, and the sine value is multiplied by the measured digital data to obtain a quadrature-phase demodulating signal.

Abstract: A dynamic delay curve generation method for an ultrasonic imaging system having the following steps: (1) obtaining three initial values of K0, N0 and &phgr;1 from a parameter decoder, where K0 is the initial delay weighted parameter, N0 is the initial delay cycle number and φ 1 = 1 - x 2 ⁢ cos 2 ⁢ θ N 0 ⁢ V 2 ⁢ T R ⁢ Δ ⁢   ⁢ t 0 ; (2) defining A=N0+&phgr;1, B=1+N0, C&

Abstract: A frequency-variation type demodulator and demodulating method. A start signal is received by a control signal apparatus. After a delay time, a control signal is output. The control signal, a start frequency, a frequency variation slope and a clock are received by an in-phase and quadrature-phase function generator. A phase value is output via mathematical calculation. According to the phase value, a cosine and sine values are obtain by checking a phase look-up table in a first and a second ROM units, respectively. The cosine value is multiplied by a measured digital data in a first multiplier to obtain an in-phase demodulating signal, and the sine value is multiplied by the measured digital data to obtain a quadrature-phase demodulating signal.

Abstract: A dynamic delay curve generation method for an ultrasonic imaging system having the following steps: (1) obtaining three initial values of K0, N0 and &phgr;1 from a parameter decoder, where K0 is the initial delay weighted parameter, N0 is the initial delay cycle number and 1 φ 1 = 1 - x 2 ⁢ cos 2 ⁢ θ N 0 ⁢ V 2 ⁢ T R ⁢ Δ ⁢   ⁢ t 0 ;