Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a

Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.

Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.

Abstract: A semiconductor device includes a substrate, a semiconductor component and a heat dissipation component. The semiconductor component is disposed on the substrate. The heat dissipation component is disposed on the substrate and having a cavity, an inlet and an outlet, wherein the inlet and the outlet communicate with the cavity.

Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A device includes an integrated circuit die attached to a substrate; a lid attached to the integrated circuit die; a sealant on the lid; a spacer structure attached to the substrate adjacent the integrated circuit die; and a cooling cover attached to the spacer structure, wherein the cooling cover extends over the lid, wherein the cooling cover attached to the lid by the sealant. In an embodiment, the device includes a ring structure on the substrate, wherein the ring structure is between the spacer structure and the integrated circuit die.

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first well region and a second well region in a substrate. The method includes forming a third well region in the substrate and between the first well region and the second well region. The method includes forming a deep well region in the substrate and under the first well region and the third well region. The method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. The method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.

Abstract: Optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. A laser die or other fill material may be used to refill the opening. The first semiconductor device is then electrically connected to an optical interposer.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.