Patents by Inventor CHEN-HUANG WANG

CHEN-HUANG WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257947
    Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 22, 2022
    Assignee: CYSTECH ELECTRONICS CORP.
    Inventors: Hsin-Yu Hsu, Yung-Chang Chen, Chen-Huang Wang
  • Patent number: 11201147
    Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 14, 2021
    Assignee: CYSTECH ELECTRONICS CORP.
    Inventors: Hsin-Yu Hsu, Chen-Huang Wang, Shih-Chieh Hung
  • Publication number: 20210358907
    Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.
    Type: Application
    Filed: August 31, 2020
    Publication date: November 18, 2021
    Inventors: HSIN-YU HSU, Chen-Huang Wang, Shih-Chieh Hung
  • Publication number: 20210351292
    Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, trench oxide layers, semiconductor layer structures, a dielectric layer structure and a metal structure. The substrate structure includes a base layer and an epitaxial layer having a plurality of trenches. A trench depth of each trench is X1 micrometer. The doped regions are respectively formed at bottoms of the trenches. The trench oxide layers are respectively formed on inner walls of the trenches. An oxide layer thickness of each trench oxide layer is X2 micrometers. X1 and X2 conform to the following relationship: 0.05X1?X2?0.25X1. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the semiconductor layer structures. The metal structure is formed on the dielectric layer structure.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: HSIN-YU HSU, YUNG-CHANG CHEN, Chen-Huang Wang
  • Publication number: 20210351291
    Abstract: A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: HSIN-YU HSU, YUNG-CHANG CHEN, Chen-Huang Wang
  • Patent number: 10790367
    Abstract: A high-voltage metal-oxide-semiconductor field-effect transistor applied to a high-voltage range includes a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of first trenches, a plurality of second trenches, a plurality of second doped regions, and a metal layer. The epitaxial layer is disposed on the substrate and used as a drain electrode. The plurality of first doped regions are disposed in the epitaxial layer. The plurality of first trenches are disposed on the plurality of doped regions in a spaced manner. Each of the first trenches has a first trench oxide layer and a first semiconductor layer which is connected to a source electrode. The plurality of second trenches are disposed between each of the first trenches in a spaced manner. Each of the second trenches has a second trench oxide layer and a second semiconductor layer which is connected to a gate electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 29, 2020
    Assignee: Cystech Electronics Corp.
    Inventors: Hsin-Yu Hsu, Chen-Huang Wang
  • Publication number: 20190288083
    Abstract: A high-voltage metal-oxide-semiconductor field-effect transistor applied to a high-voltage range includes a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of first trenches, a plurality of second trenches, a plurality of second doped regions, and a metal layer. The epitaxial layer is disposed on the substrate and used as a drain electrode. The plurality of first doped regions are disposed in the epitaxial layer. The plurality of first trenches are disposed on the plurality of doped regions in a spaced manner. Each of the first trenches has a first trench oxide layer and a first semiconductor layer which is connected to a source electrode. The plurality of second trenches are disposed between each of the first trenches in a spaced manner. Each of the second trenches has a second trench oxide layer and a second semiconductor layer which is connected to a gate electrode.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 19, 2019
    Inventors: HSIN-YU HSU, CHEN-HUANG WANG
  • Publication number: 20190280129
    Abstract: A high voltage Schottky diode applied to a high voltage range includes a substrate, an epitaxy layer, doped regions, trenches and a metal layer. The epitaxy layer is disposed on the substrate. The doped regions are disposed in the epitaxy layer. The trenches are disposed on the doped regions in a spaced manner and are in the epitaxy layer. Each trench has a trench oxide layer and a semiconductor layer. Each trench oxide layer is formed on a bottom of each trench and the side of each trench. Each semiconductor layer fills each trench. The metal layer is disposed on the epitaxy layer and become a Schottky contact with the epitaxy layer. Since each depth of the plurality of trenches is micrometer-sized and there is the configuration of the trench oxide layers, this high voltage Schottky diode can operate successfully in a high voltage range.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Inventors: HSIN-YU HSU, CHEN-HUANG WANG