Patents by Inventor Chen-Jen Kuo

Chen-Jen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240142748
    Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Ying-Jen WANG, Ya-Hsiu WU, Chen-Chi KUO, Chao-Chang HU, Yi-Ho CHEN, Che-Wei CHANG, Ko-Lun CHAO, Sin-Jhong SONG
  • Patent number: 11961810
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 6057218
    Abstract: The present invention discloses a method for simultaneously manufacturing a poly gate and a polycide gate which requires only one gate oxide layer deposition and one polysilicon layer deposition steps by incorporating a protective layer, primarily an oxide layer, which acts as a mask of a silicide. The present invention not only simplifies the process but also avoids a residual spacer in the gate. The advantages also includes widening the process window, controlling the gate channel and avoiding the gate top loss.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: May 2, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jiunn-Liang Yu, Chih-Cherng Liao, Chen-Jen Kuo