Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

Abstract: A method employed by a circuit included within a receiver apparatus and configured for performing IQ mismatch compensation when receiver apparatus is operating under data reception mode includes: transforming a data signal, which is generated by a radio frequency receiver under the data reception mode, from time domain into a plurality of frequency bin signals in frequency domain; calculating to obtain at least one frequency domain calibration parameter according to the plurality of frequency bin signals in frequency domain; and, updating at least one coefficient parameter of IQ mismatch compensation according to the obtained at least one frequency domain calibration parameter, to make IQ mismatch compensation compensate IQ mismatch based on the updated at least one coefficient parameter.

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

Abstract: A method employed by a circuit included within a receiver apparatus and configured for performing IQ mismatch compensation when receiver apparatus is operating under data reception mode includes: transforming a data signal, which is generated by a radio frequency receiver under the data reception mode, from time domain into a plurality of frequency bin signals in frequency domain; calculating to obtain at least one frequency domain calibration parameter according to the plurality of frequency bin signals in frequency domain; and, updating at least one coefficient parameter of IQ mismatch compensation according to the obtained at least one frequency domain calibration parameter, to make IQ mismatch compensation compensate IQ mismatch based on the updated at least one coefficient parameter.