Patents by Inventor Chen Jun
Chen Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240156092Abstract: The invention relates to a composition for promoting the growth of legumes. The composition includes auxin, choline chloride and ?-aminobutyric acid (GABA). The invention also relates to a method for promoting the growth of legumes.Type: ApplicationFiled: October 26, 2022Publication date: May 16, 2024Inventors: Ting-Wen CHENG, Cho-Chun HUANG, Gui-Jun Li, Kai XIA, Chen-Pang WU
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Patent number: 11978720Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.Type: GrantFiled: June 15, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai Jun Zhan, Chin-Fu Kao, Kuang-Chun Lee, Ming-Da Cheng, Chen-Shien Chen
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Patent number: 11942445Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.Type: GrantFiled: August 23, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20240090230Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.Type: ApplicationFiled: January 9, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20240049470Abstract: A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventors: Chen-Jun Wu, Sun-Yi Chang, Sheng-Chih Lai, Chung-Te Lin
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Publication number: 20240038294Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.Type: ApplicationFiled: August 1, 2022Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chen-Jun Wu, Yun-Feng Kao, Sheng-Chih Lai, Katherine H. Chiang, Chung-Te Lin
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Publication number: 20230328980Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20230328996Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drainType: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
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Publication number: 20230262985Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.Type: ApplicationFiled: April 27, 2023Publication date: August 17, 2023Inventors: Chen-Jun Wu, Yu-Wei Jiang, Sheng-Chih Lai
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Patent number: 11723199Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11723210Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drainType: GrantFiled: May 28, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
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Patent number: 11672123Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.Type: GrantFiled: February 5, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Jun Wu, Yu-Wei Jiang, Sheng-Chih Lai
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Publication number: 20220285384Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.Type: ApplicationFiled: March 3, 2021Publication date: September 8, 2022Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20220285395Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drainType: ApplicationFiled: May 28, 2021Publication date: September 8, 2022Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
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Patent number: 11321734Abstract: An information processing method, a server, and a computer storage medium are provided. The method includes: generating a first information identification code according to first information, the first information representing an information source; providing the first information identification code to a terminal; receiving a first request from the terminal and allowing a terminal user of the terminal to follow an information service, the first request carrying the first information; and recording the first information and tracking and obtaining conversion information of the information source according to the first information.Type: GrantFiled: June 18, 2018Date of Patent: May 3, 2022Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Peng Yin, Qian Wang, Jun Xian Guo, Dong Yang, Can Zheng, Yuan Wang, Rong Yan, Hui Liu, Chen Jun Yang, Cheng Chen, Zhou Zhou, Shao Gang Tang
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Patent number: 10381094Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).Type: GrantFiled: October 11, 2016Date of Patent: August 13, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chen-Jun Wu, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue
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Publication number: 20180300752Abstract: An information processing method, a server, and a computer storage medium are provided. The method includes: generating a first information identification code according to first information, the first information representing an information source; providing the first information identification code to a terminal; receiving a first request from the terminal and allowing a terminal user of the terminal to follow an information service, the first request carrying the first information; and recording the first information and tracking and obtaining conversion information of the information source according to the first information.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Peng YIN, Qian WANG, Jun Xian GUO, Dong YANG, Can ZHENG, Yuan WANG, Rong YAN, Hui LIU, Chen Jun YANG, Cheng CHEN, Zhou ZHOU, Shao Gang TANG
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Publication number: 20180102177Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chen-Jun WU, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting LUE
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Patent number: D809231Type: GrantFiled: December 9, 2015Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Haibo Luo, Masato Suzuki, Keiichi Minamide, Hirohisa Miyazaki, Chen Cui, Lijun Qi, Mitsuhiro Shigeri, Jing Xie, Chen Jun
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Patent number: D809722Type: GrantFiled: December 9, 2015Date of Patent: February 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Haibo Luo, Masato Suzuki, Keiichi Minamide, Hirohisa Miyazaki, Chen Cui, Lijun Qi, Mitsuhiro Shigeri, Jing Xie, Chen Jun