Abstract: The present invention provides a dithering and directional modulation-based frame rate conversion apparatus comprising: a directional delta modulation generator configured to receive a plurality of input color data representing a plurality of input color components of an input pixel color and generate a plurality of modulated data for the plurality of input color data respectively; and a plurality of dithering modules configured to perform K-bit dithering conversion on the plurality of input color data respectively to generate a plurality of output color data for representing a plurality of output color components of an output pixel color with a color depth of K bits per component, where K is an integer equal to or great than 1. The present invention can allow display to support frame rates higher than its standard configuration without observable color depth degradation.

Abstract: A display system circuitry capable of saving power consumption includes a display panel and a driver circuitry. In particular, the display panel includes a plurality of source electrodes with a plurality of data lines and a plurality of gate electrodes further includes a gate driver which is directly incorporated into a thin film transistor array to form Gate on Array (GOA) electrode, a source electrode transmitting a plurality of data driving signals, a gate electrode transmitting gate driving signals, a VCOM electrode transmitting voltage driving signals, a display electrode transmitting displaying driving signals. The driver circuitry includes a display driver IC which includes a source driver operably configured to drive the source electrode and gate control to control gate driver output, and a touch driver IC configured to generate the touch scan signal from a touch sensor.

Abstract: A display system circuitry capable of saving power consumption includes a display panel and a driver circuitry. In particular, the display panel includes a plurality of source electrodes with a plurality of data lines and a plurality of gate electrodes further includes a gate driver which is directly incorporated into a thin film transistor array to form Gate on Array (GOA) electrode, a source electrode transmitting a plurality of data driving signals, a gate electrode transmitting gate driving signals, a VCOM electrode transmitting voltage driving signals, a display electrode transmitting displaying driving signals. The driver circuitry includes a display driver IC which includes a source driver operably configured to drive the source electrode and gate control to control gate driver output, and a touch driver IC configured to generate the touch scan signal from a touch sensor.

Abstract: A touch display system, and a driving apparatus and a driving method thereof are provided. The driving apparatus includes at least one gate driver, at least one source driver, a common voltage generator and a switching circuit. The gate driver drives the gate lines by turns in a scanning order. An output terminal of the common voltage generator outputs a common voltage. The switching circuit electrically connects a plurality of common lines of the touch display panel to the output terminal of the common voltage generator by turns according to the scanning order of the gate driver.

Abstract: A half-ratio charge pump circuit includes a flying capacitor electrically coupled between a first node and a second node. Eight switches are controlled to carry out first to fourth operating phases during which charges are stored on and transferred from the flying capacitor, thereby generating a positive output voltage at approximately half the positive input voltage, and generating a negative output voltage at approximately half the negative input voltage.

Abstract: A half-ratio charge pump circuit includes a flying capacitor electrically coupled between a first node and a second node. Eight switches are controlled to carry out first to fourth operating phases during which charges are stored on and transferred from the flying capacitor, thereby generating a positive output voltage at approximately half the positive input voltage, and generating a negative output voltage at approximately half the negative input voltage.

Abstract: A multiplexer includes: a first switch unit coupled between a first input terminal and an output terminal and including a series connection of first and second switches; a second switch unit coupled between a second input terminal and the output terminal; and a third switch unit coupled to a third input terminal and a common node between the first and second switches. Different first and second voltages, and a third voltage greater than one of the first and second voltages and less than the other one of the first and second voltage are applied respectively to the first, second and third input terminals. The multiplexer is operable between a first mode, where the first voltage is transmitted to the output terminal, and a second mode, where the second voltage is transmitted to the output terminal and the third voltage is transmitted to the common node between the first and second switches.

Abstract: A voltage multiplying circuit comprising: a first capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the first capacitor is selectively coupled to a first voltage or a second voltage, and the second terminal is selectively coupled to the first voltage or a fourth voltage; a second capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the second capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the second capacitor is selectively coupled to a third voltage or the fourth voltage; and a third capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the third capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the third capacitor is selectively coupled to a third voltage or the fourth voltage.

Abstract: A charge pump includes a timing signal generator for generating complementary first and second timing signals, and a voltage booster including a plurality of voltage boosting circuits. Each of the voltage boosting circuits includes input and output terminals, first and second capacitors each having first and second ends, and a switch module. The switch module is controllable to make or break electrical connection between the second end of the first capacitor and each of the input and output terminals and between the second end of the second capacitor and each of the input and output terminals. The first end of each of the first and second capacitors of a first one of the voltage boosting circuits receives a respective one of the first and second timing signals.

Abstract: A fan structure comprises a stator module and a fan frame, the stator module comprises a fixing plate, an insulating holder, and a stator core. The fixing plate has a first surface, an opposite second surface and at least one fixing portion formed on the second surface and having a first engaging portion. The insulating holder has a first side facing the second surface of the fixing plate, an opposite second side and at least one catching member formed on the first side and having a second engaging portion. The stator core is coupled to the insulating holder. The fan frame has a base, the base is located between the fixing plate and the insulating holder, wherein the first engaging portion of the fixing member is engaged with the second engaging portion of the catching member.

Abstract: A digital-to-analog converting device converts an N-bit digital input signal into an analog signal using M reference voltages, where N>3 and M=2(N?2)+1, and includes: a decoding unit operable based on third to Nth bits of the digital input signal and reference voltages to output first and second decoding voltages; and an output unit operable based on the first and second decoding voltages and first and second bits of the digital input signal to generate the analog signal. The decoding unit includes K first selectors and a second selector consisting of first and second decoding circuits, where K=2(N?3)+1.

Abstract: A method for reducing resonance energy of an LCD panel includes providing a plurality of driving signal patterns, each defining a non-overlap area width of a synchronization signal and a scan-line charging frequency, and determining an order of the plurality of driving signal patterns to modulate driving signals of the LCD panel accordingly.

Abstract: A charge pump circuit includes an input end, a first reservoir capacitor, a second reservoir capacitor, a first output end, a second output end, and a charge pump unit. The input end is utilized for receiving an input voltage. The charge pump unit includes a first flying capacitor, a second capacitor, a plurality of switches, and a control unit. The control unit is utilized for controlling on/off state of the plurality of switches so that the first flying capacitor provides a positive charge pump voltage to the first output end or a negative charge pump voltage to the second output and the second flying capacitor provides a positive charge pump voltage to the first output end through charge and discharge process.

Abstract: A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner.

Abstract: A voltage multiplying circuit comprising: a first capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the first capacitor is selectively coupled to a first voltage or a second voltage, and the second terminal is selectively coupled to the first voltage or a fourth voltage; a second capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the second capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the second capacitor is selectively coupled to a third voltage or the fourth voltage; and a third capacitor, comprising a first terminal and a second terminal, wherein the first terminal of the third capacitor is selectively coupled to the second voltage or the fourth voltage, and the second terminal of the third capacitor is selectively coupled to a third voltage or the fourth voltage.

Abstract: A positioning structure for a stator assembly of a fan motor has a fan base and a stator assembly. The fan base has a central hub projected thereon for connecting to one end of an axial tube. The fan base is further formed with a plurality of first engagement portions surrounding a hub base of an outer peripheral surface of the central hub. The stator assembly has an axial hole sleeved on the axial tube and a plurality of second engagement portions which can be engaged with the first engagement portions. Thus, the stator assembly can be rapidly and stably installed on the fan base.

Abstract: A fan structure comprises a stator module and a fan frame, the stator module comprises a fixing plate, an insulating holder, and a stator core. The fixing plate has a first surface, an opposite second surface and at least one fixing portion formed on the second surface and having a first engaging portion. The insulating holder has a first side facing the second surface of the fixing plate, an opposite second side and at least one catching member formed on the first side and having a second engaging portion. The stator core is coupled to the insulating holder. The fan frame has a base, the base is located between the fixing plate and the insulating holder, wherein the first engaging portion of the fixing member is engaged with the second engaging portion of the catching member.

Abstract: A multiplexer includes: a first switch unit coupled between a first input terminal and an output terminal and including a series connection of first and second switches ; a second switch unit coupled between a second input terminal and the output terminal; and a third switch unit coupled to a third input terminal and a common node between the first and second switches. Different first and second voltages, and a third voltage greater than one of the first and second voltages and less than the other one of the first and second voltage are applied respectively to the first, second and third input terminals. The multiplexer is operable between a first mode, where the first voltage is transmitted to the output terminal, and a second mode, where the second voltage is transmitted to the output terminal and the third voltage is transmitted to the common node between the first and second switches.

Abstract: A charge pump circuit includes an input end, a first reservoir capacitor, a second reservoir capacitor, a first output end, a second output end, and a charge pump unit. The input end is utilized for receiving an input voltage. The charge pump unit includes a first flying capacitor, a second capacitor, a plurality of switches, and a control unit. The control unit is utilized for controlling on/off state of the plurality of switches so that the first flying capacitor provides a positive charge pump voltage to the first output end or a negative charge pump voltage to the second output and the second flying capacitor provides a positive charge pump voltage to the first output end through charge and discharge process.

Abstract: A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner.