Abstract: According to one embodiment, a power supply circuit includes a switching element to which a drive signal is supplied, a control value generating circuit that compares an output voltage and a reference voltage to generate a control value, and a comparison circuit that compares a feedback current and the control value. The power supply circuit has a generating circuit that generates a clock signal having a constant period in a PWM control mode and a clock signal according to the output voltage in a PFM control mode. The control value of the control value generating circuit is changed so that averages of the feedback current before and after the control mode switching become equal.

Abstract: According to one embodiment, a power circuit includes an input terminal 1 to which a DC input voltage is applied, an output terminal 2, a first DC/DC converter which receives the DC input voltage and supplies a first phase output current to the output terminal 2, a second DC/DC converter which supplies an output current lower than the first phase output current to the output terminal in a second phase which is different from the first phase, and a controller which controls operations of the first and second DC/DC converters.

Abstract: A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value.

Abstract: According to an embodiment, a power supply circuit is provided. The power supply circuit includes a switching transistor which is controlled to be ON/OFF by a PWM signal, and a mode switching control circuit configured to switch a control mode between peak current mode control and valley current mode control depending on the length of an ON time of the PWM signal which drives the switching transistor.

Abstract: According to an embodiment, provided is a power circuit including: a switching transistor connected between an input terminal and an output terminal; a drive circuit configured to output a drive signal that controls on/off of the switching transistor; an error calculation circuit configured to output an error value between the output voltage and reference voltage; a determination circuit configured to compare a reference value obtained from the error value with a predetermined threshold value and then output a control signal; and a control circuit configured to control a frequency of the drive signal in response to the control signal.

Abstract: According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.

Abstract: According to one embodiment, the power circuit includes a first feedback loop which feedbacks information on an output voltage and a second feedback loop which feedbacks information on a load current. When the load current is smaller than a predetermined threshold value, the second feedback loop is blocked and a PWM signal is generated using data of a feedback current signal which is stored before blocking the second feedback loop.

Abstract: A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a DCDC control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit.

Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.

Abstract: A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a DCDC control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit.

Abstract: According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.

Abstract: A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value.

Abstract: According to one embodiment, a power supply circuit includes a switching control unit that compares a DA converted value of the high order bit of a digital compensation value calculated from an output voltage of a smoothing circuit with a detection value of a current flowing into the smoothing circuit and controls the switching of a switching element on the basis of a signal obtained by shifting the timing of the comparison result on the basis of the low order bit of the digital compensation value.

Abstract: According to one embodiment, the power circuit includes a first feedback loop which feedbacks information on an output voltage and a second feedback loop which feedbacks information on a load current. When the load current is smaller than a predetermined threshold value, the second feedback loop is blocked and a PWM signal is generated using data of a feedback current signal which is stored before blocking the second feedback loop.

Abstract: According to one embodiment, a power circuit includes an input terminal 1 to which a DC input voltage is applied, an output terminal 2, a first DCDC converter which receives the DC input voltage and supplies a first phase output current to the output terminal 2, a second DCDC converter which supplies an output current lower than the first phase output current to the output terminal in a second phase which is different from the first phase, and a controller which controls operations of the first and second DCDC converters.

Abstract: A semiconductor device includes a first semiconductor chip which includes a first power supply terminal and into which a circuit block which is operated by a power supply voltage supplied to the first power supply terminal is integrated, a power circuit that includes switching transistors and supplies the power supply voltage to the first power supply terminal, and a DCDC control unit that is formed on the first semiconductor chip and generates a control signal for controlling the turning on and off of the switching transistors in response to an information signal from the circuit block and a voltage information signal corresponding to an output voltage from the power circuit.

Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.

Abstract: In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.

Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.

Abstract: In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.