Abstract: A process for intermetal SOG/SOP dielectric planarization without having effect is described. First, a silicon-rich oxide (SRO) layer is formed on a substrate surface. Next, a metal layer and an antireflective coating (ARC) layer are sequentially deposited over the SRO layer. The metal layer and ARC layer are then etched to define metal patterns by the conventional lithography and etching techniques. Next, an Ozone-TEOS (O.sub.3 -TEOS) layer and a SOG layer are then formed over the entire substrate surface. Next, the O.sub.3 -TEOS layer and SOG layer are subjected to etching back treatment to obtain a planar substrate surface which only has a small portion of the O.sub.3 -TEOS layer covered on the substrate surface. The etching back treatment can be PEB, TEB or CMP techniques. Finally, a passivation layer is deposited over the remaining of O.sub.3 -TEOS layer.

Abstract: A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. Next, a very thin layer of silicon dioxide is formed over the silicon substrate surface, followed by depositing a layer of rough oxide with proper grain size overlaying the silicon dioxide layer. By using rough oxide grains as an etching mask, the silicon dioxide layer and the silicon substrate underneath are spontaneously etched to form multiple trenches in the isolation region. Next, the rough oxide grains and silicon dioxide layers are stripped. Then, filed oxidation is performed to complete the field oxide isolation formation.