Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.

Abstract: A bandwidth allocation device includes a buffer device, a main scheduler, an oversubscription scheduler, a multiplexer and a detecting device. The buffer device is arranged to receive first data units from first ports and second data units from second ports and accordingly output these data units. The main scheduler is configured to schedule the first data units and accordingly output the first data units in sequence. The oversubscription scheduler is configured to schedule the second data units and accordingly output the second data units in sequence. The multiplexer is controlled by the main scheduler to select the first data units outputted by the main scheduler and the second data units outputted by the oversubscription scheduler for outputting. The detecting device is arranged to generate power-related information which the main scheduler relies on to control the multiplexer.

Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.

Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.

Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.

Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.