Abstract: An electroplating method is disclosed that selectively deposits a greater thickness of a metal or alloy layer on a region of wafer that has a higher thickness loss during a subsequent chemical mechanical polish process. A paddle assembly has three rectangular sides joined at their edges to form a triangle shape from an end view, and a notch in a bottom side that faces a wafer during the plating process. The notch extends along second and third paddle sides to a height up to about 50% of the paddle thickness. The thickness in a K-block region that has two sides formed parallel to the wafer flat is selectively increased by aligning a first side of the paddle notch side directly over one K-block side and aligning a second notch side directly over a second K-block side during a paddle movement cycle. The notch may be rectangular shaped or tapered.

Abstract: An electroplating method is disclosed that selectively deposits a greater thickness of a metal or alloy layer on a region of wafer that has a higher thickness loss during a subsequent chemical mechanical polish process. A paddle assembly has three rectangular sides joined at their edges to form a triangle shape from an end view, and a notch in a bottom side that faces a wafer during the plating process. The notch extends along second and third paddle sides to a height up to about 50% of the paddle thickness. The thickness in a K-block region that has two sides formed parallel to the wafer flat is selectively increased by aligning a first side of the paddle notch side directly over one K-block side and aligning a second notch side directly over a second K-block side during a paddle movement cycle. The notch may be rectangular shaped or tapered.

Abstract: A method of creating a black box timing model for a digital circuit. The digital circuit is characterized by a block model having at least one input and at least one output. The method determines a delay statement for the output of the block model. The method also determines an input set-up constraint for the input of the block model. The input set-up constraint is based upon the delay statement. The model is then used with a static timing analyzer to accurately model a flow-through circuit.

Abstract: A method of creating a black box timing model for a digital circuit. The digital circuit is characterized by a block model having at least one input and at least one output. The method determines a delay statement for the output of the block model. The method also determines an input set-up constraint for the input of the block model. The input set-up constraint is based upon the delay statement. The model is then used with a static timing analyzer to accurately model a flow-through circuit.

Abstract: A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.

Abstract: A system and method for automatically selecting decoupling capacitors for an electronic device. The system determines a localized drive strength for each component in the electronic device. Based on a summation of drive strengths for components in a given area of the electronic device, the system determines whether a decoupling capacitor is necessary to provide local power bus stability.