Patents by Inventor Chen-Liang Chu
Chen-Liang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150295055Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.Type: ApplicationFiled: June 26, 2015Publication date: October 15, 2015Inventors: Chen-Liang CHU, Fei-Yuh CHEN, Yi-Sheng CHEN, Shih-Kuang HSIAO, Chun Lin TSAI, Kong-Beng THEI
-
Publication number: 20150279951Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: June 12, 2015Publication date: October 1, 2015Inventors: Chen-Liang Chu, Fei-Yun Chen, Chih-Wen Yao
-
Publication number: 20150249144Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yuh Chen, Kong-Beng Thei
-
Patent number: 9099556Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.Type: GrantFiled: August 19, 2011Date of Patent: August 4, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai, Kong-Beng Thei
-
Patent number: 9070663Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: GrantFiled: August 16, 2013Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
-
Patent number: 9035380Abstract: An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.Type: GrantFiled: November 27, 2012Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yun Chen, Kong-Beng Thei
-
Publication number: 20140273376Abstract: A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area where low voltage devices are to be formed as well as gate structures of high voltage devices while performing high energy implants for the high voltage devices. Another method of semiconductor fabrication includes performing high energy implants for high voltage devices through a patterned photoresist where the photoresist is patterned prior to forming gate structures for high voltage devices and prior to forming gate structures for low voltage devices. After the high energy implants are performed, subsequent processing is performed to form high voltage devices and low voltage devices. High voltage device and low voltage devices are thus formed in a CMOS process without need for additional masks.Type: ApplicationFiled: February 20, 2014Publication date: September 18, 2014Inventors: Alexander Kalnitsky, Kong-Beng Thei, Chien-Chih Chou, Chen-Liang Chu, Hsiao-Chin Tuan
-
Publication number: 20140145261Abstract: An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.Type: ApplicationFiled: November 27, 2012Publication date: May 29, 2014Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yun Chen, Kong-Beng Thei
-
Patent number: 8673712Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.Type: GrantFiled: July 20, 2012Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yuh Chen, Kong-Beng Thei
-
Publication number: 20140021539Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yun Chen, Kong-Beng Thei
-
Publication number: 20130337644Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: August 16, 2013Publication date: December 19, 2013Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
-
Patent number: 8513712Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: GrantFiled: September 28, 2009Date of Patent: August 20, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
-
Publication number: 20130043533Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang CHU, Fei-Yuh CHEN, Yi-Sheng CHEN, Shih-Kuang HSIAO, Chun Lin TSAI, Kong-Beng THEI
-
Patent number: 8377787Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: GrantFiled: June 8, 2011Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
-
Patent number: 8183626Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: GrantFiled: February 14, 2011Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
-
Publication number: 20110237041Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
-
Patent number: 7977743Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: GrantFiled: February 25, 2009Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
-
Publication number: 20110163375Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: ApplicationFiled: February 14, 2011Publication date: July 7, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
-
Publication number: 20110073962Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
-
Patent number: 7888734Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: GrantFiled: December 4, 2008Date of Patent: February 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen