Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.

Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.

Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.

Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.