Patents by Inventor Chen-Lin Chao

Chen-Lin Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112928
    Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Hsuan Lee, Chen-Hao Wu, Chun-Hung Liao, Huang-Lin Chao
  • Publication number: 20240113056
    Abstract: A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.
    Type: Application
    Filed: March 3, 2023
    Publication date: April 4, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Chih-Wei Tseng, Jui Lin Chao
  • Publication number: 20240103236
    Abstract: A method includes forming an optical engine, which includes a photonic die. The photonic die further includes a grating coupler. The method further includes forming a fiber unit including a fiber platform having a groove, and an optical fiber attached to the fiber platform. The optical fiber extends into the groove. The fiber platform further includes a reflector. The fiber unit is attached to the optical engine, and the reflector is configured to deflect a light beam, so that the light beam emitted by a first one of the optical fiber and the grating coupler is received by a second one of the optical fiber and the grating coupler.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 28, 2024
    Inventors: Chih-Wei Tseng, Jui Lin Chao, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20240107781
    Abstract: Optical devices and methods of manufacture are presented in which an opening is formed within a first semiconductor device and then bonded to other optical devices. A laser die or other fill material may be used to refill the opening. The first semiconductor device is then electrically connected to an optical interposer.
    Type: Application
    Filed: March 28, 2023
    Publication date: March 28, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Jui Lin Chao
  • Publication number: 20240103218
    Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 28, 2024
    Inventors: Hsing-Kuo Hsia, Jui Lin Chao, Chen-Hua Yu, Chih-Hao Yu, Shih-Peng Tai
  • Patent number: 11942373
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20240094469
    Abstract: A method includes patterning a top silicon layer in a substrate to form a plurality of photonic devices. The substrate includes the top silicon layer, a first dielectric layer under the top silicon layer, and a semiconductor layer under the first dielectric layer. The method further includes forming a second dielectric layer to embed the plurality of photonic devices therein, forming an interconnect structure over and signally coupling to the plurality of photonic devices, bonding an electronic die to the interconnect structure, thinning the semiconductor layer, and patterning the semiconductor layer that has been thinned to form openings. The openings are filled with a dielectric material to form dielectric regions. Through-vias are formed to penetrate through the dielectric regions to electrically couple to the interconnect structure.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 21, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Jui Lin Chao
  • Publication number: 20240085621
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. A waveguide is formed in the interconnect structure. An optical-engine based interconnect component is bonded to the interconnect structure. The optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 14, 2024
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Chih-Wei Tseng, Jui Lin Chao
  • Publication number: 20040193301
    Abstract: System and method for controlling the use of control wafers in a semiconductor fabrication line with load balancing and resource minimization. A preferred embodiment comprises a control wafer manager (for example, control wafer manager 605) and an inventory manager (for example, inventory manager 630). The control wafer manager uses a fabrication process dependency graph (for example, fabrication process dependency graph 407) to help determine where a control wafer may be able to go after it has completed its current process step. The inventory manager uses available inventory at each process step to assist in the decision process. Finally, a check-in process is used to ensure accurate inventory control.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Chen-Lin Chao, Wei-Kuo Yen, Jiunh-Yih Lee